A High Performance Silicon-on-Insulator LDMOSTT Using Linearly Increasing Thickness Techniques
GUO Yu-Feng1,2, WANG Zhi-Gong1, SHEU Gene3, CHENG Jian-Bing2
1Institute of RF- & OE-ICs, Southeast University, Nanjing 210096 2School of Electronics Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing 210003 3Department of Computer Science & Information Engineering, Asia University, Taichung 41354
A High Performance Silicon-on-Insulator LDMOSTT Using Linearly Increasing Thickness Techniques
GUO Yu-Feng1,2, WANG Zhi-Gong1, SHEU Gene3, CHENG Jian-Bing2
1Institute of RF- & OE-ICs, Southeast University, Nanjing 210096 2School of Electronics Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing 210003 3Department of Computer Science & Information Engineering, Asia University, Taichung 41354
We present a new technique to achieve uniform lateral electric field and maximum breakdown voltage in lateral double-diffused metal-oxide-semiconductor transistors fabricated on silicon-on-insulator substrates. A linearly increasing drift-region thickness from the source to the drain is employed to improve the electric field distribution in the devices. Compared to the lateral linear doping technique and the reduced surface field technique, two-dimensional numerical simulations show that the new device exhibits reduced specific on-resistance, maximum off- and on-state breakdown voltages, superior quasi-saturation characteristics and improved safe operating area.
We present a new technique to achieve uniform lateral electric field and maximum breakdown voltage in lateral double-diffused metal-oxide-semiconductor transistors fabricated on silicon-on-insulator substrates. A linearly increasing drift-region thickness from the source to the drain is employed to improve the electric field distribution in the devices. Compared to the lateral linear doping technique and the reduced surface field technique, two-dimensional numerical simulations show that the new device exhibits reduced specific on-resistance, maximum off- and on-state breakdown voltages, superior quasi-saturation characteristics and improved safe operating area.
[1] Zhang T, Lu H L, Zhang Y M, Zhang Y M and Ye L H 2008 Chin. Phys. Lett. 25 1818 [2] Yang F, Jin K J, Lu H B, He M and Yang G Z 2009 Chin. Phys. Lett. 26 077301 [3] Qiao M, Zhang B, Li Z J and Fang J 2007 Electron. Lett. 43 1231 [4] Huang Y S and Baliga B J 1991 Proceedings of International Symposium on Power Semiconductor Devices and ICs (Baltimore, USA 22-24 April 1991) p 27 [5] Cheng J B, Zhang B, Duan B X and LI Z J 2008 Chin. Phys. Lett. 25 262 [6] Guo Y F, Li Z J and Zhang B 2006 Microelectron. J. 37 861 [7] Merchant S, Arnold E, Baumgart H, Pein H and Pinker R 1991 Proceedings of International Symposium on Power Semiconductor Devices and ICs (Baltimore, USA 22-24 April 1991) p 31 [8] Zhang S D, Sin J K O and Laim T M L 1999 IEEE Trans. Electron. Devices 46 1036 [9] Baliga B J 1989 IEEE Electron. Device Lett. 10 455 [10] Darwish M N 1999 IEEE Trans. Electron. Devices 44 1117 [11] Aarts A C T and Kloosterman W J 2006 IEEE Trans. Electron. Devices 53 897 [12] Baliga B J 1995 Power Semiconductor Devices (Boston: PWS) chap 7 p 335 [13] Letavic T and Simpson M 2001 US Patent 6221737B1 [14] Monteiro D W, Akhza L O, Sarro P M and Vdovin G 2003 Opt. Express 41 2244
2010, Vol. 27 
