1Integrated Circuit Advanced Process Center, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029 2Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029
Abstract：Strained-Si$_{0.73}$Ge$_{0.27}$ channels are successfully integrated with high-$\kappa $/metal gates in p-type metal-oxide- semiconductor field effect transistors (pMOSFETs) using the replacement post-gate process. A silicon cap and oxide inter layers are inserted between Si$_{0.73}$Ge$_{0.27}$ and high-$\kappa$ dielectric to improve the interface. The fabricated Si$_{0.73}$Ge$_{0.27}$ pMOSFETs with gate length of 30 nm exhibit good performance with high drive current ($\sim$428 $\mu$A/μm at $V_{\rm DD}=1$ V) and suppressed short-channel effects (DIBL$\sim $77 mV/V and SS$\sim$90 mV/decade). It is found that the enhancement of effective hole mobility is up to 200% in long-gate-length Si$_{0.73}$Ge$_{0.27}$-channel pMOSFETs compared with the corresponding silicon transistors. The improvement of device performance is reduced due to strain relaxation as the gate length decreases, while 26% increase of the drive current is still obtained for 30-nm-gate-length Si$_{0.73}$Ge$_{0.27}$ devices.
Lee J C, Cho H J, Kang C S, Rhee S J, Kim Y H, Choi R, Kang C Y, Choi C H and Abkar M 2003 IEDM Tech. Dig. p 95
[11]
Ragnarsson L A, Pantisano L, Kaushik V, Saito S I, Shimamoto Y, Gendt S D and Heyns M 2003 IEDM Tech. Dig. p 87
[12]
Morioka A, Watanabe H, Miyamura M, Tatsumi T, Saitoh M, Ogura T, Iwamoto T, Ikarashi T, Saito Y, Okada Y, Watanabe H, Mochiduki Y and Mogami T 2003 VLSI Tech. Dig. p 165
Weber O, Damlencourt J F, Andrieu F, Ducroquet F, Ernst T, Hartmann J M, Papon A M, Renault O, Guillaumot B and Deleonibus S 2006 IEEE Trans. Electron Devices53 449
Deshpande V, Djara V, O'Connor E, Hashemi P, Balakrishnan K, Sousa M, Caimi D, Olziersky A, Czornomaz L and Fompeyrine J 2015 IEDM Tech. Dig. p 209
[23]
Eneman G, Yamaguchi S, Ortolland C, Takeoka S, Witters L, Chiarella T, Favia P, Hikavyy A, Mitard J, Kobayashi M, Krom R, Bender H, Tseng J, Wang W E, Vandervorst W, Loo R, Absil P, Biesemans S and Hoffmann T 2010 VLSI Tech. Dig. p 41
2016, Vol. 33 
