| CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES |
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Positive Bias Temperature Instability Degradation of Buried InGaAs Channel nMOSFETs with InGaP Barrier Layer and Al$_{2}$O$_{3}$ Dielectric |
| Sheng-Kai Wang1,2, Lei Ma2,3, Hu-Dong Chang1,2, Bing Sun1,2, Yu-Yu Su2, Le Zhong4, Hai-Ou Li3, Zhi Jin2, Xin-Yu Liu2, Hong-Gang Liu1,2** |
1Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029
2High-Frequency High-Voltage Device and Integrated Circuits R&D Center, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029
3Guangxi Experiment Center of Information Science, Guilin University of Electronic Technology, Guilin 541004
4Microsystem and Terahertz Research Center, China Academy of Engineering Physics, Chengdu 610200
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| Cite this article: |
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Sheng-Kai Wang, Lei Ma, Hu-Dong Chang et al 2017 Chin. Phys. Lett. 34 057301 |
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Abstract Positive bias temperature instability stress induced interface trap density in a buried InGaAs channel metal-oxide-semiconductor field-effect transistor with a InGaP barrier layer and Al$_{2}$O$_{3}$ dielectric is investigated. Well behaved split $C$–$V$ characteristics with small capacitance frequency dispersion are confirmed after the insertion of the InGaP barrier layer. The direct-current $I_{\rm d}$–$V_{\rm g}$ measurements show both degradations of positive gate voltage shift and sub-threshold swing in the sub-threshold region, and degradation of positive $\Delta V_{\rm g}$ in the on-current region. The $I_{\rm d}$–$V_{\rm g}$ degradation during the positive bias temperature instability tests is mainly contributed by the generation of near interface acceptor traps under stress. Specifically, the stress induced acceptor traps contain both permanent and recoverable traps. Compared with surface channel InGaAs devices, stress induced recoverable donor traps are negligible in the buried channel ones.
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Received: 30 November 2016
Published: 29 April 2017
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| PACS: |
73.40.Qv
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(Metal-insulator-semiconductor structures (including semiconductor-to-insulator))
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71.55.Eq
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(III-V semiconductors)
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77.55.D-
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| Fund: Supported by the National Science and Technology Major Project of China under Grant No 2011ZX02708-003, the National Natural Science Foundation of China under Grant No 61504165, and the Opening Project of Key Laboratory of Microelectronics Devices and Integrated Technology of Institute of Microelectronics of Chinese Academy of Sciences. |
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