Chin. Phys. Lett.  2018, Vol. 35 Issue (2): 027302    DOI: 10.1088/0256-307X/35/2/027302
CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES |
Concise Modeling of Amorphous Dual-Gate In-Ga-Zn-O Thin-Film Transistors for Integrated Circuit Designs
Can Li, Cong-Wei Liao**, Tian-Bao Yu, Jian-Yuan Ke, Sheng-Xiang Huang, Lian-Wen Deng
School of Physics and Electronics, Central South University, Changsha 410083
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Can Li, Cong-Wei Liao, Tian-Bao Yu et al  2018 Chin. Phys. Lett. 35 027302
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Abstract An analytical model for current–voltage behavior of amorphous In-Ga-Zn-O thin-film transistors (a-IGZO TFTs) with dual-gate structures is developed. The unified expressions for synchronous and asynchronous operating modes are derived on the basis of channel charges, which are controlled by gate voltage. It is proven that the threshold voltage of asynchronous dual-gate IGZO TFTs is adjusted in proportion to the ratio of top insulating capacitance to the bottom insulating capacitance $(C_{\rm TI}/C_{\rm BI})$. Incorporating the proposed model with Verilog-A, a touch-sensing circuit using dual-gate structure is investigated by SPICE simulations. Comparison shows that the touch sensitivity is increased by the dual-gate IGZO TFT structure.
Received: 29 August 2017      Published: 23 January 2018
PACS:  73.40.Qv (Metal-insulator-semiconductor structures (including semiconductor-to-insulator))  
  71.23.An (Theories and models; localized states)  
  85.60.Pg (Display systems)  
Fund: Supported by the National Key Research and Development Program of China under Grant No 2017YFA0204600, the National Natural Science Foundation of China under Grant No 61404002, and the Science and Technology Project of Hunan Province under Grant No 2015JC3041.
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https://cpl.iphy.ac.cn/10.1088/0256-307X/35/2/027302       OR      https://cpl.iphy.ac.cn/Y2018/V35/I2/027302
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Can Li
Cong-Wei Liao
Tian-Bao Yu
Jian-Yuan Ke
Sheng-Xiang Huang
Lian-Wen Deng
[1]Qian H M et al 2015 Chin. Phys. B 24 077307
[2]Tang L F et al 2016 Chin. Phys. Lett. 33 038502
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[4]Son K S et al 2010 IEEE Electron Device Lett. 31 219
[5]Liu F et al 2016 Appl. Phys. A 122 311
[6]Baek G et al 2011 IEEE Trans. Electron Devices 58 4344
[7]Wang C C, Hu Z J, He X, Liao C W and Zhang S D 2016 IEEE Trans. Electron Devices 63 3800
[8]Nakamura T 2011 J. Soc. Info. Display 19 639
[9]Cheu W J, Tai Y H, Lin C H and Hsiao P H 2017 SID 17 Digest March 23–25 2017 Los Angeles, USA p 738
[10]Brown C, Hadwen B and Kato H 2007 IEEE International Solid-State Circuits Conference, February 12 2007 San Francisco, USA p 132
[11]Qin T, Huang S X, Liao C W, Yu T B and Deng L W 2017 Acta. Phys. Sin. 66 097101 (in Chinese)
[12]Abe K, Takahashi K, Sato A, Kumomi H, Nomura K, Kamiya T, Kanicki J and Hosono H 2012 IEEE Trans. Electron Devices 59 1928
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[16]Lee S, Striakhilev D, Jeon S and Nathan A 2014 IEEE Trans. Electron Devices 35 84
[17]Baek G and Kanicki J 2012 J. Soc. Info. Display 20 237
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