Low Specific On-Resistance SOI LDMOS with Non-Depleted Embedded P-Island and Dual Trench Gate
Jie Fan, Sheng-Ming Sun, Hai-Zhu Wang, Yong-Gang Zou**
State Key Laboratory of High Power Semiconductor Laser, Changchun University of Science and Technology, Changchun 130022
Abstract ：A new silicon-on-insulator (SOI) trench lateral double-diffused metal oxide semiconductor (LDMOS) with a reduced specific on-resistance $R_{\rm on,sp}$ is presented. The structure features a non-depleted embedded p-type island (EP) and dual vertical trench gate (DG) (EP-DG SOI). First, the optimized doping concentration of drift region is increased due to the assisted depletion effect of EP. Secondly, the dual conduction channel is provided by the DG when the EP-DG SOI is in the on-state. The increased optimized doping concentration of the drift region and the dual conduction channel result in a dramatic reduction in $R_{\rm on,sp}$. The mechanism of the EP is analyzed, and the characteristics of $R_{\rm on,sp}$ and breakdown voltage (BV) are discussed. Compared with conventional trench gate SOI LDMOS, the EP-DG SOI decreases $R_{\rm on,sp}$ by 47.1% and increases BV from 196 V to 212 V at the same cell pitch by simulation.
收稿日期: 2017-09-12
出版日期: 2018-02-25
:
85.30.De
(Semiconductor-device characterization, design, and modeling)
85.30.Mn
(Junction breakdown and tunneling devices (including resonance tunneling devices))
85.30.Tv
(Field effect devices)
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2018, Vol. 35 
