Chin. Phys. Lett.  2018, Vol. 35 Issue (5): 057302    DOI: 10.1088/0256-307X/35/5/057302
CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES |
Improvement of Operation Characteristics for MONOS Charge Trapping Flash Memory with SiGe Buried Channel
Zhao-Zhao Hou1,2, Gui-Lei Wang1,2, Jia-Xin Yao1,2, Qing-Zhu Zhang1, Hua-Xiang Yin1,2**
1Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029
2University of Chinese Academy of Sciences, Beijing 100049
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Zhao-Zhao Hou, Gui-Lei Wang, Jia-Xin Yao et al  2018 Chin. Phys. Lett. 35 057302
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Abstract We propose and investigate a novel metal/SiO$_{2}$/Si$_{3}$N$_{4}$/SiO$_{2}$/SiGe charge trapping flash memory structure (named as MONOS), utilizing SiGe as the buried channel. The fabricated memory device demonstrates excellent program-erasable characteristics attributed to the fact that more carriers are generated by the smaller bandgap of SiGe during program/erase operations. A flat-band voltage shift 2.8 V can be obtained by programming at +11 V for 100 μs. Meanwhile, the memory device exhibits a large memory window of $\sim$7.17 V under $\pm$12 V sweeping voltage, and a negligible charge loss of 18% after 10$^{4}$ s' retention. In addition, the leakage current density is lower than $2.52\times10^{-7}$ A$\cdot$cm$^{-2}$ below a gate breakdown voltage of 12.5 V. Investigation of leakage current-voltage indicates that the Schottky emission is the predominant conduction mechanisms for leakage current. These desirable characteristics are ascribed to the higher trap density of the Si$_{3}$N$_{4}$ charge trapping layer and the better quality of the interface between the SiO$_{2}$ tunneling layer and the SiGe buried channel. Therefore, the application of the SiGe buried channel is very promising to construct 3D charge trapping NAND flash devices with improved operation characteristics.
Received: 01 February 2018      Published: 30 April 2018
PACS:  73.40.Qv (Metal-insulator-semiconductor structures (including semiconductor-to-insulator))  
  77.55.dj (For nonsilicon electronics (Ge, III-V, II-VI, organic electronics))  
  77.55.Px (Epitaxial and superlattice films)  
  72.20.Jv (Charge carriers: generation, recombination, lifetime, and trapping)  
Fund: Supported by the National Science and Technology Major Project of China under Grant No 2013ZX02303007, the National Key Research and Development Program of China under Grant No 2016YFA0301701, and the Youth Innovation Promotion Association of the Chinese Academy of Sciences under Grant No 2016112.
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https://cpl.iphy.ac.cn/10.1088/0256-307X/35/5/057302       OR      https://cpl.iphy.ac.cn/Y2018/V35/I5/057302
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Zhao-Zhao Hou
Gui-Lei Wang
Jia-Xin Yao
Qing-Zhu Zhang
Hua-Xiang Yin
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