| CONDENSED MATTER: STRUCTURE, MECHANICAL AND THERMAL PROPERTIES |
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Formation of Co-implanted Silicon Ultra-Shallow Junctions for Low Thermal Budget Applications |
| Rehana Mustafa1, S. Ahmed2,3*, E. U. Khan3,4 |
1Department of Physics, International Islamic University, Islamabad, Pakistan
2Advanced Electronics Laboratory, Faculty of Engineering & Technology, International Islamic University Islamabad, Pakistan
3Center for Emerging Sciences, Engineering and Technology, Islamabad, Pakistan
4Department of Physics, Gomal University, D. I. Khan, Pakistan
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| Cite this article: |
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Rehana Mustafa, S. Ahmed, E. U. Khan 2013 Chin. Phys. Lett. 30 016101 |
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Abstract We present a systematic study to create ultra-shallow junctions in n-type silicon substrates and investigate both pre- and post-annealing processes to create a processing strategy for potential applications in nano-devices. Starting wafers were co-implanted with indium and C atoms at energies of 70 keV and 10 keV, respectively. A carefully chosen implantation schedule provides an abrupt ultra-shallow junction between 17 and 43 nm with suppressed sheet resistance and appropriate retained sheet carrier concentration at low thermal budget. A defect doping matrix, primarily the behavior and movement of co-implant generated interstitials at different annealing temperatures, may be engineered to form sufficiently activated ultra-shallow devices.
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Received: 25 May 2012
Published: 04 March 2013
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| PACS: |
61.72.uf
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(Ge and Si)
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61.72.Cc
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(Kinetics of defect formation and annealing)
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73.40.-c
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(Electronic transport in interface structures)
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