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Memory Effect of Metal--Insulator--Silicon Capacitors with SiO2/HfO2/Al2O3 Dielectrics |
| LIAO Zhong-Wei;HUANG Yue;ZHANG Min;SUN Qing-Qing;DING Shi-Jin;ZHANG Wei |
| State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433 |
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| Cite this article: |
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LIAO Zhong-Wei, HUANG Yue, ZHANG Min et al 2008 Chin. Phys. Lett. 25 1908-1911 |
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Abstract Charge trapping characteristics of the metal--insulator--silicon (MIS) capacitors with SiO2/HfO2/Al2O3 stacked dielectrics are investigated for memory applications. A capacitance-voltage hysteresis memory window as large as 7.3V is achieved for the gate voltage sweeping of ±12V, and a flat-band voltage shift of 1.5V is observed in terms of programming under 5V and 1ms.Furthermore, the time- and voltage-dependent charge trapping
characteristics are also demonstrated, the former is related to charge trapping saturation and the latter is ascribed to variable tunnelling barriers for electron injecting and discharging under different voltages.
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| Keywords:
85.25.Hv
77.55.+f
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Received: 13 December 2007
Published: 29 April 2008
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| PACS: |
85.25.Hv
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(Superconducting logic elements and memory devices; microelectronic circuits)
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77.55.+f
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