| CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES |
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Improved Programming Efficiency through Additional Boron Implantation at the Active Area Edge in 90nm Localized Charge-Trapping Non-volatile Memory |
XU Yue1,3, YAN Feng1, CHEN Dun-Jun1, SHI Yi1, WANG Yong-Gang2, LI Zhi-Guo2, YANG Fan2, WANG Jos-Hua2, LIN Peter2, CHANG Jian-Guang2 |
| 1Department of Physics, Nanjing University, Nanjing 210093 2Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai 201203 3College of Electronic Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing 210003 |
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| Cite this article: |
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XU Yue, YAN Feng, CHEN Dun-Jun et al 2010 Chin. Phys. Lett. 27 067201 |
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Abstract As the scaling-down of non-volatile memory (NVM) cells continues, the impact of shallow trench isolation (STI) on NVM cells becomes more severe. It has been observed in the 90 nm localized charge-trapping non-volatile memory (NROMTM) that the programming efficiency of edge cells adjacent to STI is remarkably lower than that of other cells when channel hot electron injection is applied. Boron segregation is found to be mainly responsible for the low programming efficiency of edge cells. Meanwhile, an additional boron implantation of 10\circ tilt at the active area edge as a new solution to solve this problem is developed.
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| Keywords:
72.80.Cw
73.40.Qv
73.50.Lw
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Received: 15 January 2010
Published: 25 May 2010
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| PACS: |
72.80.Cw
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(Elemental semiconductors)
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73.40.Qv
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(Metal-insulator-semiconductor structures (including semiconductor-to-insulator))
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73.50.Lw
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(Thermoelectric effects)
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[1] Machala C, Wise R, Mercer D and Chatterjee A 1997 International Conference on Simulation of Semiconductor Processes and Device (Piscataway USA 8-10 September 1997) p 141
[2] Kuo P, Hoyt J L and Gibbons J F 95 Appl. Phys. Lett. 66 580
[3] Miyamoto M, Ohta H and Kumagai Y 2004 IEEE Trans. Electron Devices 51 440
[4] Kahng A B, Sharma P and Topaloglu R O 2007 IEEE Conference on Computer-Aided Design (San Jose, CA, USA 5-8 November 2007) p 83
[5] Ghetti A, Benvenuti A, Molteni G, Alberici S, Soncini V and Pavan A 2004 IEEE International Electron Device Meeting (San Francisco, CA, USA 13-15 December 2004) p 983
[6] Wang H, Xu H P E, Wai T N, Fukumoto K, Ishikawa A, Furukawa Y, Imai H, Naito T, Sato N, Sakai K, Tamura S and Takasuka K 2008 IEEE Electron Device Lett. 29 1239
[7] Li Z, Yang F, Wang J, Lin P, Chang J G, Wang Y G, Yi C and Yan F 2009 International Semiconductor Technology Conference (Shanghai, China 19-20 March 2009) p 43
[8] Eitan B, Pavan P, Bloom I Aloni E, Frommer A and Finzi D 2000 IEEE Electron. Device Lett. 21 543
[9] Pavan P et al 1997 Proc. IEEE 85 1248
[10] Hu C 1978 IEEE International Electron Device Meeting (Washington, DC 4-6 December 1978) p 22
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