Controllable Ultra Low- k by Via-Typed Air Gap with the Better Design Margin for Logic Devices below 45nm Node
CHOI Youn-Ok1, KIM Sang-Yong2
1Department of Electrical Engineering, Chosun University, #375, Seosuk-dong, Dong-gu, Gwangju 501-759, Republic of Korea 2Department of Semiconductor System, Korea Polytechnic College IV, Cheongju 361-857, Republic of Korea
Controllable Ultra Low- k by Via-Typed Air Gap with the Better Design Margin for Logic Devices below 45nm Node
CHOI Youn-Ok1, KIM Sang-Yong2
1Department of Electrical Engineering, Chosun University, #375, Seosuk-dong, Dong-gu, Gwangju 501-759, Republic of Korea 2Department of Semiconductor System, Korea Polytechnic College IV, Cheongju 361-857, Republic of Korea
By changing the air gap to a via-typed air gap, the height of the air gap is reduced up to about 50% compared to the height of the trench-typed air gap. The controllable (1≤k <2.9) ultra low-k is also easily fabricated by adjusting the space of the via-typed air gap. The via-typed air gap makes the design margin better due to its lower height in the dense and narrow lines.
By changing the air gap to a via-typed air gap, the height of the air gap is reduced up to about 50% compared to the height of the trench-typed air gap. The controllable (1≤k <2.9) ultra low-k is also easily fabricated by adjusting the space of the via-typed air gap. The via-typed air gap makes the design margin better due to its lower height in the dense and narrow lines.
CHOI Youn-Ok;KIM Sang-Yong. Controllable Ultra Low- k by Via-Typed Air Gap with the Better Design Margin for Logic Devices below 45nm Node[J]. 中国物理快报, 2010, 27(9): 97701-097701.
CHOI Youn-Ok, KIM Sang-Yong. Controllable Ultra Low- k by Via-Typed Air Gap with the Better Design Margin for Logic Devices below 45nm Node. Chin. Phys. Lett., 2010, 27(9): 97701-097701.
[1] Faguet J, Lee E, Junjun L, Brcka J and Akiyama O 2009 Proceedings of IEEE International Interconnect Technology Conference IITC 2009 p 35 [2] Gallitrea M, Farcy A, Blampey B, Bermonda C, Flécheta B and Ancey P 2010 Microelectron. Eng. 87 321 [3] Park H, Kraatz M, Im J, Kastenmeier B and Ho P S 2009 Advanced Nanoscale ULSI Interconnects: Fundamentals and Applications (New York: Springer) [4] Daamen R, Bancken P H L, Nguyen V H, Humbert A, Verheijden G J A M and Hoofman R J O M 2007 Microelectron. Eng. 84 2177 [5] Piontek A, Vanhoucke T, Van Huylenbroeck S, Choi L J, Hurkx G A M, Hijzen E and Decoutere S 2007 Semicond. Sci. Technol. 22 S9 [6] Chan K and Gleason K K 2006 J. Electrochem. Soc. 153 C223 [7] Ueda T, Harada T, Ueki A, Kido S, Tomita K, Kanda Y, Sasaki T, Tsuji H, Furuhashi T, Kabe T, Shibata J, Iwasaki A, Izumitani J, Kawano Y and Matsumoto S 2009 Tenth International Workshop on Stress-Induced Phenomena in Metallization 2009 172
2010, Vol. 27 
