⇦Chinese Physics Letters, 2018, Vol. 35, No. 4, Article code 047302⇨ Resistivity and Radio-Frequency Properties of Two-Generation Trap-Rich Silicon-on-Insulator Substrates * Lei Zhu(朱雷)1,2,3, Yong-Wei Chang(常永伟)1,3, Nan Gao(高楠)1,3, Xin Su(苏鑫)1,3, YeMin Dong(董业民)1,3, Lu Fei(费璐)1,3,4, Xing Wei(魏星)1,4**, Xi Wang(王曦)1,2,3 Affiliations 1State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050 2School of Physical Science and Technology, Shanghaitech University, Shanghai 200031 3University of Chinese Academy of Sciences, Beijing 100049 4Shanghai Simgui Technology Co., Ltd., Shanghai 201815 Received 29 December 2017, online 13 March 2018 ^*Supported by the National Natural Science Foundation of China under Grant Nos 61376021 and 61674159, and the Program of Shanghai Academic/Technology Research Leader under Grant No 17XD1424500.
^**Corresponding author. Email: xwei@mail.sim.ac.cn Citation Text: Zhu L, Chang Y W, Gao N, Su X and Dong Y et al 2018 Chin. Phys. Lett. 35 047302 Abstract Crystal morphologies and resistivity of polysilicon trap-rich layers of two-generation trap-rich silicon-on-insulator (TR-SOI) substrates are studied. It is found that the resistivity of the trap-rich layer of generation 2 (TR-G2) is higher than that of generation 1 (TR-G1), although the crystal morphologies of the trap rich layers are the same. In addition, the rf performance of two-generation TR-SOI substrates is investigated by coplanar waveguide lines and inductors. The results show that both the rf loss and the second harmonic distortion of TR-G2 are smaller than those of TR-G1. These results can be attributed to the higher resistivity values of both the trap-rich layer and the high-resistivity silicon (HR-Si) substrate of TR-G2. Moreover, the rf performance of the TR-SOI substrate with thicker buried oxide is slightly better. The second harmonics of various TR-SOI substrates are simulated and evaluated with the harmonic quality factor model as well. It can be predicted that the TR-SOI substrate will see further improvement in rf performance if the resistivities of both the trap-rich layer and HR-Si substrate increase. DOI:10.1088/0256-307X/35/4/047302 PACS:73.40.Ty, 84.32.-y, 84.32.Ff © 2018 Chinese Physics Society Article Text High-resistivity silicon-on-insulator (HR-SOI) wafer has been proven to be a solution for rf applications such as antenna switches in the front-end module (FEM) of handsets.[1,2] However, it has been previously shown that HR-SOI substrates suffer from the parasitic surface conduction (PSC) effect due to the fixed charges in the buried oxide (BOX) layer,[3,4] which limits their rf performance. For many years, researchers have introduced several surface-passivation approaches to improve the rf performance of HR-SOI substrates. The approaches include proton or argon ion implantation, silicon etching by TMAH, and deposition of a layer of amorphous silicon ($\alpha$-Si) or polycrystalline silicon (poly-Si).[5-12] Among these technologies, the poly-Si film stands out and becomes the industrialized solution. This is because poly-Si has numerous grain boundaries and defects, which can effectively trap the free carriers caused by the PSC effect.[9] Moreover, poly-Si is compatible with the mature integrated circuit (IC) manufacturing process, and its thermal stability is very good.[13] In 2005, Raskin et al. developed the TR-SOI substrate.[11] Poly-Si film is used as the trap-rich layer for the TR-SOI substrate. Since then, the TR-SOI substrate has become the mainstream technology in the mobile communication world.[14] As we are moving to a 5G network, the data traffic is growing rapidly. The requirement for linearity is even more stringent on most critical FEM blocks.[15] To meet the requirements for the incoming 5G network, rf performance of TR-SOI substrate needs to be improved furthermore. In this study, firstly, the physical properties and resistivity of two-generation TR-SOI substrates are investigated, and then both small- and large-signal characteristics of passive devices manufactured on the two-generation TR-SOI substrates are measured and analyzed. Finally, ways to improve the rf performance of TR-SOI substrates are predicted by the harmonic quality factor (HQF) model. Two-generation 200 mm TR-SOI wafers, namely TR-G1 and TR-G2, are investigated in this work. Two BOX thicknesses are considered. The BOX thicknesses of both generations are 100 nm and 400 nm, respectively. The cross-sectional view and material properties of TR-SOI substrates are summarized in Fig. 1(a) and Table 1. All wafers are manufactured using the Smart-Cut$^{\rm TM}$ technology.[14,16]

**Table 1.** Material properties of the TR-SOI substrates.
rf-SOI	$\rho$ (k$\Omega\cdot$cm)	$t_{\rm BOX}$	$t_{\rm TR}$	$t_{\rm HR-Si}$
substrates	of HR-Si	(μm)	(μm)	(μm)
TR-G1-1	4	0.1	1.8	725
TR-G1-2	4	0.4	1.8	725
TR-G2-1	10	0.1	1.8	725
TR-G2-2	10	0.4	1.8	725

To characterize the surface topographies and resistivity values of trap-rich layers, the top silicon and BOX layers are removed by TMAH solution and HF solution, respectively. The rf performance of TR-SOI substrates is investigated using coplanar waveguide (CPW) lines and spiral inductors.[17] A layer of 0.5 μm aluminum and 0.5 μm gold is patterned on top of the BOX layers to form 50 $\Omega$ CPW lines and 1 nH inductors. Figures 1(b) and 1(c) show the schematic drawings of CPW line and inductor, respectively. The CPW line dimensions are $W =32$ μm (width of the central conductor), $S=12$ μm (slot space between the central conductor and the ground conductor), $W_{\rm g} =208$ μm (width of the ground conductors), and $L =2176$ μm (length of the conductors). The one-turn inductor dimensions are $R_{1} =410$ μm (outer radius of the inductor), and $R_{2} =250$ μm (inner radius of the inductor).

Fig. 1. (a) Cross-sectional view of TR-SOI wafer. (b) Top view of CPW line with rf pads. (c) Top view of one-turn inductor.

On-wafer small and large signal measurements are performed on each passive device using a dedicated setup based on a cascade12000B-M probe station.[17]

Fig. 2. XTEM [(a), (b)] and AFM [(c), (d)] pictures of trap-rich layers of TR-G1 [(a), (c)] and TR-G2 [(b), (d)] substrates.

Cross-sectional transmission electron microscopy (XTEM) and atomic force microscopy (AFM) are used to characterize the cross-sectional and surface morphologies of poly-Si layers. The pictures are shown in Fig. 2. Figures 2(a) and 2(b) depict that the grains of poly-Si layers of both the TR-SOI substrates are typical columnar structures. Moreover, in this field of view, the grains of both poly-Si layers are non-uniform. The rms surface roughness of poly-Si layers of TR-G1 and of TR-G2 on $5\times5$ μm$^{2}$ squares are 0.378 nm and 0.354 nm, respectively. Because of their excellent smooth surfaces, the grain sizes can be figured out clearly. Although with arbitrary sizes, the average grain size of them is about 1 μm (Figs. 2(c) and 2(d)). Preliminary results actually show that the material properties of the trap-rich layers of the two-generation of TR-SOI substrates are the same. As a qualified trap-rich layer of TR-SOI substrate, the poly-Si layer needs not only abundant grain boundaries to trap the carriers induced by PSC, but also maintains high resistivity itself. The resistivity of poly-Si is highly important as it is the part of the substrate that is just below the BOX and is very close to the rf devices. When a large rf signal is propagating along the rf devices integrated on the TR-SOI substrate, the signal will also penetrate into the poly-Si layer. This requires that the poly-Si layer has high resistivity. In this work, the resistivity values of TR-SOI substrates are measured by the spreading resistance profiling (SRP).[18] The measured depth is 5 μm from the top poly-Si layer into the p-type HR-Si substrate.

Fig. 3. Resistivity profiles of TR-SOI substrates.

As presented in Fig. 3, the resistivity of HR-Si of TR-G2 is 10 k$\Omega\cdot$cm, while the resistivity of HR-Si of TR-G1 is only about 4 k$\Omega\cdot$cm. For either curve in Fig. 3, it is interesting that the resistivities of both poly-Si and HR-Si gradually drop as approaching the poly-Si/HR-Si interface. Moreover, the resistivity of the poly-Si layer of TR-G2 is larger than that of TR-G1. It is known that the resistivity of the poly-Si film is related to grain size and doping concentration while the resistivity of single crystal silicon purely depends on the doping concentration at room temperature.[19-21] Since the grain sizes of poly-Si layers of TR-G2 and TR-G1 are identical (Fig. 2), it is the dopants that dominate the resistivity values of them. Although the deposited poly-Si film is undoped first, it can be doped by impurities introduced in the subsequent bonding process. Boron is a common dopant in SOI manufacturing processes. Boron concentration of samples in this work is measured using secondary ion mass spectroscopy (SIMS). The results are shown in Fig. 4. It should be mentioned that the boron concentration in HR-Si away from the poly-Si/HR-Si interface is lower than the limit of detection. For either curve in Fig. 4, it is clearly seen that boron diffuses from the poly-Si layer into the HR-Si substrate. In the HR-Si substrate, boron concentration decreases rapidly. This leads to the increase of resistivity of HR-Si from a few hundreds of $\Omega\cdot$cm to k$\Omega$$\cdot$cm. In the poly-Si layer, however, boron concentration shows a slight change while the resistivity of poly-Si near the poly-Si/Si interface decreases. This is related to SRP measurement itself that the multilayer model is utilized to extract the local resistivity value. The substrate is subdivided into a vast number of sublayers and the resistivity at etch depth takes into account the effectiveness of all the sublayers, which suggests that the measured resistivity value at the etch depth will vary in the case of substrates with non-uniform resistivity values.[18] In our case, the measured resistivity of the poly-Si layer is pulled down by the subjacent HR-Si substrate, and a dip at the poly-Si/HR-Si interface forms.

Fig. 4. Boron concentration in TR-SOI substrates.

An Agilent 4-port PNA-X vector network analyzer is used to measure the CPW lines' $S$-Parameters up to 6 GHz. TRL calibration is used to de-embed the unwanted parasitics caused by the rf pads in Fig. 1(b). The attenuation coefficient of the CPW lines is extracted from the $S$-parameters. It is shown in Fig. 5 that the losses of all TR-SOI substrates are very small. Furthermore, the losses of TR-G2 are slightly lower than that of TR-G1 when the frequency is higher than 1 GHz. This is because the resistivity of TR-G2 is higher than TR-G1. However, losses of TR-G2 and TR-G1 with different BOX thicknesses present no differences. The second harmonics of CPW lines on various substrates are also compared. The fundamental frequency is 900 MHz. Figure 6 shows that the second harmonic of TR-G2 offers a 10 dBm improvement than TR-G1. Harmonics, along with losses, clearly indicate that rf performance of TR-SOI substrates can improve by increasing the resistivity of both poly-Si and HR-Si substrate. Moreover, the second harmonic of TR-G2 or TR-G1 with thicker BOX thickness is slightly better before saturation. This can be explained by the theory that while sharing the same silicon substrate (poly-Si and HR-Si), the effective resistivity of TR-SOI substrate with thicker BOX thickness is higher.[22] However, the extracted losses of CPW lines on these substrates are not sensitive to the change of effective resistivity (Fig. 3). To understand the correlation between losses and oxide thicknesses, one-turn inductors are studied. The results will be discussed in the following.

Fig. 5. Measured attenuation coefficients $\alpha$ of CPW lines on various substrates.

Fig. 6. Measured second harmonic distortions (2nd harmonic) of CPW lines on various substrates, with freq-fundamental equaling 900 MHz.

In this work, we design and fabricate one-port inductors on various TR-SOI substrates and compare their properties. The parameters of interest are the inductance ($L$) and the maximum quality factor ($Q_{\max}$). The inductance values of the inductors versus frequency are presented in Fig. 7, and the corresponding quality factor values are presented in Fig. 8. We can clearly see from Fig. 7 that the inductance is almost the same for all inductors on these different substrates. The low-frequency inductance is 1 nH. Figure 8 shows that the inductors have their $Q_{\max}$ at frequency beyond 8.5 GHz. The values of $Q_{\max}$ of these inductors are higher than 60. The value of $Q$ of TR-G2 is larger than that of TR-G1. Moreover, for a single generation, $Q$ of the TR-SOI substrate with thicker BOX thickness is slightly higher. Figures 7 and 8 indicate that for either generation, the loss of TR-SOI substrate with thicker BOX thickness is slightly lower. This is consistent with the second harmonics results plotted in Fig. 6.

Fig. 7. Inductance values of inductors on various substrates.

Fig. 8. Quality factor values of inductors on various substrates.

As a result, compared with the BOX thickness, the resistivity values of the poly-Si layer and the HR-Si substrate have a more significant impact on the rf performance of the TR-SOI substrate. Traditionally, measuring the level of harmonic distortions generated by a signal injected on a CPW line is used to quantify the level of nonlinearity of the material. Raskin has developed a proprietary algorithm, which integrates the SRP profile weighted by the depth of the electrical field and matches it to the second harmonic generated through a CPW line. This parameter is called the harmonic quality factor (HQF).[19,22] Based on the above analysis, the resistivity values of poly-Si and the HR-Si play the most important roles in determining the nonlinearities of the TR-SOI substrates. Thus we use the HQF model to simulate the nonlinearities of TR-SOI substrates with different resistivities. In our simulation, the resistivity values of poly-Si and HR-Si are the variables. To simplify the model, the thickness of poly-Si is fixed at 2 μm, and the resistivity of the poly-Si layer remains unchanged over thickness. The simulated result is shown in Fig. 9. We can see that when the resistivity of the poly-Si layer is less than 100 $\Omega\cdot$cm, no matter how high the resistivity of HR-Si substrate is, the HQF of the TR-SOI substrates is higher than $-$80 dBm. This means that the resistivity of the poly-Si layer is dominant in this case. Furthermore, once the resistivity of poly-Si layer is higher than 100 $\Omega\cdot$cm, the resistivity of HR substrate dominates. For the same resistivity of the poly-Si layer, the HQF decreases with increasing the resistivity of HR-Si substrate. For example, fixing the resistivity of poly-Si layer at 4 k$\Omega\cdot$cm, the HQF can reach $-$100 dBm if the resistivity of the HR-Si layer is 15 k$\Omega\cdot$cm, while the HQF is as high as $-$70 dBm if the resistivity of the HR-Si layer is 1 k$\Omega\cdot$cm. According to the simulated results, it can be obtained that the better linearity of TR-SOI can be attributed to its higher resistivity of the poly-Si layer and resistivity of HR-Si substrate. This suggests that increasing the resistivity values of the poly-Si layer and the HR-Si substrate is an effective solution to improve the linearity of TR-SOI substrates.

Fig. 9. Simulated HQF of various substrates with different resistivity values of poly-Si ($\rho _{\rm poly-Si}$) and HR-Si ($\rho _{\rm HR-Si}$).

In summary, material features and the related rf properties of two-generation TR-SOI substrates have been investigated. The nonlinearities are simulated using the HQF model. The results predict that the higher the resistivity values of poly-Si layer and the HR-Si substrate of TR-SOI substrates are, the better the rf performance will be. References Modeling of nonlinear active regions in TLM (distributed circuits)Attenuation mechanisms of aluminum millimeter-wave coplanar waveguides on siliconIntegrated antennas on Si with over 100 GHz performance, fabricated using an optimized proton implantation processSuper self-aligned GaAs RF switch IC with 0.25 dB extremely low insertion loss for mobile communication systemsEffective resistivity of fully-processed SOI substratesLow-loss CPW lines on surface stabilized high-resistivity siliconNew substrate passivation method dedicated to HR SOI wafer fabrication with increased substrate resistivityCharacteristics of trenched coplanar waveguide for high-resistivity Si MMIC applicationsEffects of Low Boron Concentration on Electrical Properties of Commercial Trap-Rich High Resistivity SOI SubstrateA Spreading Resistance Technique for Resistivity Measurements on SiliconThe electrical properties of polycrystalline silicon filmsResistivity of Doped Polycrystalline Silicon FilmsRF Harmonic Distortion of CPW Lines on HR-Si and Trap-Rich HR-Si Substrates

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