⇦Chinese Physics Letters, 2016, Vol. 33, No. 9, Article code 096101 New Method of Total Ionizing Dose Compact Modeling in Partially Depleted Silicon-on-Insulator MOSFETs * Jian-Qiang Huang(黄建强)1,2, Wei-Wei He(何伟伟)1,2, Jing Chen(陈静)1**, Jie-Xin Luo(罗杰馨)1, Kai Lu(吕凯)1,2, Zhan Chai(柴展)1 Affiliations 1State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050 2University of Chinese Academy of Sciences, Beijing 100049 Received 11 April 2016 *Supported by the National Natural Science Foundation of China under Grant Nos 61404151 and 61574153.
**Corresponding author. Email: jchen@mail.sim.ac.cn Citation Text: Huang J Q, He W W, Chen J, Luo J X and Lu K et al 2016 Chin. Phys. Lett. 33 096101 Abstract On the basis of a detailed discussion of the development of total ionizing dose (TID) effect model, a new commercial-model-independent TID modeling approach for partially depleted silicon-on-insulator metal-oxide-semiconductor field effect transistors is developed. An exponential approximation is proposed to simplify the trap charge calculation. Irradiation experiments with $^{60}$Co gamma rays for IO and core devices are performed to validate the simulation results. An excellent agreement of measurement with the simulation results is observed. DOI:10.1088/0256-307X/33/9/096101 PACS:61.80.Ed, 61.82.-d, 85.30.De © 2016 Chinese Physics Society Article Text Compact models such as BSIM, PSP, EKV, HiSIM are widely used in the design of intergrated circuits (ICs) to shorten the development cycle and to reduce the costs of the tests. These models accurately simulate circuits through precise mathematical expressions to calculate the physical effects in metal-oxide-semiconductor field effect transistors (MOSFETs). With the development of space technology, bio-medical and nuclear technology, electronic devices and circuits which are vulnerable to radiation have become an important issue. However, the commercial compact model does not contain the total ionizing dose (TID) effect which is one of the radiation effects caused by the irradiation exposure in the MOS structure. As the MOS transistor is exposed to high-energy ionizing irradiation, electron-hole pairs are created uniformly and induce the buildup of trap charge throughout the oxide,[1] which can lead to device degradation. It has been suggested that in the MOS structure, leakage path occurs between the source and drain in the field oxide when the traps build up in soft oxide.[2] Moreover, buildup charges are strongly dependent on the electrical field in the oxide,[3] and the TID model has been investigated[4-8] by analysis of charge distribution in gate oxide, corner, and shallow-trench-insulation (STI). Technology-computer-aid-design (TCAD) simulation[9,10] and compact modeling[4,5,7,8] were studied by both calculating the trap charge at or near the semiconductor/oxide interface to obtain threshold voltage shift. Zebrev et al.[8] suggested that the parasitic field oxide leakage current can be treated as numbers of parallel transistors added to subcircuits. The current expression of these compact models using integral operation cost more time in the simulation. In addition, parameters are extracted by TCAD simulation[4] or special test structures[5] lead to the long period of parameter extraction procedure. In this Letter, we focus on studies of silicon-on-insulator (SOI) devices, which have been extensively investigated due to their radiation immune structure including good ability to protect the single event effect.[1] We present a compact SOI MOSFET model to simulate the TID effect, considering drain-induced-barrier lowing (DIBL), the body effect in $V_{\rm th}$ expression. Based on the BSIM3.3 model, we modify the formula of $V_{\rm th}$ and $I_{\rm ds}$. Different areas of the body factor are analyzed to avoid integral operation, and the exponential approximation approach is presented to solve the problem of trapping charges distribution. We integrate the TID model into the commercial model by Verilog-A. The comparison of simulation and measurement result is presented, including the fitting parameters. Preliminary results[9,11] suggest that different regions present different radiation responses. The sidewall of STI leads to the increase of the leakage current for MOS devices at off-state, and the corner between gate oxide and STI can affect the subthreshold character, also called the hump effect. In addition, the buried oxide in SOI can produce leakage current at substrate voltage of zero at high dose, and this current can append to the front gate transistor. In this work, the leakage current induced by the TID effect in the buried oxide under 1000 krad(Si) for core devices and 200 krad(Si) for IO devices can be ignored by our back-gate TID experiments. Moreover, the partially depleted SOI MOSFETs have no coupling effect between back-gate and front-gate transistors in the TID effect. Thus it can presumably divide the region into three including intrinsic MOS, corner and STI. As the traps captured at and near semiconductor/oxide interface, the traps can decrease, and increase the threshold voltage of NMOS, and PMOS, respectively. Moreover, the traps will also result in subthreshold slope swing and carrier mobility degradation.[12]
cpl-33-9-096101-fig1.png
Fig. 1. Illustration of (a) NMOS layout, and (b) cross-section of STI edge excluding the buried oxide and substrate, the electrical field from gate to underlying Si in the whole oxide including gate, corner and STI oxide, respectively.
As illustrated in Fig. 1(a), to study the leakage path between source and drain, the cross section along the dashed line is shown to represent intrinsic MOS (I), corner (II), and STI (III) in Fig. 1(b), additionally, buried oxide and substrate layer are excluded by the above discussion. The gate for intrinsic MOS can act as a parasitic gate to source/drain. Equation (1) shows the threshold voltage directly proportional to the oxide thickness, which can be expressed as $$\begin{align} V'_{\rm th}=\,&V'_{\rm th0}+\gamma'(\sqrt{\phi_{\rm s}-V_{\rm bs}} - \sqrt{\phi_{\rm s}}) \\ &-\sigma' V_{\rm ds}-\frac{Q'_{\rm trap}}{C'_{\rm ox}},~~ \tag {1} \end{align} $$ where $V'_{\rm th0}$ is the ideal threshold voltage, $\gamma'$ is the body factor for the specified region, $\phi_{\rm s}$ is the surface potential at strong inversion, $\sigma'$ is the DIBL coefficient, $Q'_{\rm trap}$ is the trap charges at and near the semiconductor/oxide interface, $C'_{\rm ox}$ is the effective oxide capacitor per unit area, $V_{\rm bs}$ is the voltage between body and source, and $V_{\rm ds}$ is the voltage between drain and source. Thus the field oxide in STI and corner oxide can be treated as different parasitic transistors with different $V_{\rm th}$, due to their oxide thickness. If the order of $V_{\rm th}$ for two parasitic transistors decreases to the order of the main transistor, then the above two parasitic transistors parallel to the intrinsic MOS will be negligible. For simplicity, the threshold voltage for MOS devices can be derived,[13] and the superscripts denote the parasitic transistor parameters in the following. As depicted in Fig. 1(b), the dashed lines among regions I, II, and III in the silicon body are the depletion region boundary. For further discussion, $\gamma_{\rm m}$, $\gamma_{\rm c}$, and $\gamma_{\rm s}$ are denoted body factors of regions I, II, and III, respectively. Regions I and III will be extended by the greater gate voltage and the trap build up in the oxide, which result in the boundary of region I and III enclose region II, and then, the body factor of region II weakened. Thus $\gamma_{\rm c}$ is smaller than $\gamma_{\rm m}$ and $\gamma_{\rm s}$. This is the practical rule for parameter extraction in the following. In Eq. (1), we define $\phi_{\rm s}=2v_{\rm t}\ln(N_{\rm ch}/n_{\rm i})$, where $v_{\rm t}$ is the thermal voltage, $N_{\rm ch}$ is the channel doping concentration, and $n_{\rm i}$ denotes the intrinsic carrier concentration. In addition, the DIBL coefficient $\sigma'$ can be derived from the previous studies[14] on the DIBL effect, $$\begin{align} \sigma'=\frac{\varepsilon_{\rm si}}{\pi C'_{\rm ox} L}=\frac{\varepsilon_{\rm si} t'_{\rm ox}}{\varepsilon_{\rm ox} \pi L},~~ \tag {2} \end{align} $$ where $\varepsilon_{\rm si}$ and $\varepsilon_{\rm ox}$ are silicon and oxide dielectric constant, respectively, $t'_{\rm ox}$ is the effective oxide thickness for the parasitic transistor, and $L$ is the channel length for the intrinsic transistor. The relationship between dose and trap charges is[3] $$\begin{align} \frac{Q'_{\rm trap}}{C'_{\rm ox}}=\,&\frac{q g_{0}t'_{\rm ox}f_{\rm y}(E_{\rm ox})D}{2C'_{\rm ox}}\\ =\,&\frac {q g_{0}}{2\varepsilon_{\rm ox}}f_{\rm y}(E_{\rm ox})D{t'_{\rm ox}}^2,~~ \tag {3} \end{align} $$ where $q$ is the charge constant, $g_0$ is the pair density generated per rad for a specified material, for SiO$_2$, $g_0=8.1 \times 10^{12}$ pair/cm$^3$, $f_{\rm y}(E_{\rm ox})$ is the electro-hole pair yield function ranging from 0 to 1, and $D$ is the radiation dose in SiO$_{2}$. As the dose increases, electrical field through the oxide will be decreased as the hole appending an extra electrical field. As is expected, previous works show that $f_{\rm y}(E_{\rm ox})D$ is complicated because its electrical field expression usually contains some integral operation. On the other hand, Mclean et al.[3] suggested that the threshold voltage shifts linearly as the dose increases, while it reaches a levelling off at a high dose due to the saturation of the trapped hole density. For convenience, we assume the exponential approximation to characterize this behavior, thus items associated with charge buildup can be expressed as $$\begin{align} f_{\rm y}(E_{\rm ox})D=k'_1\Big[1-\exp\Big(-\frac{D}{\tau'}\Big)\Big],~~ \tag {4} \end{align} $$ where $\tau'$ is the charge distribution parameter, and $k'_1$ is the scale parameter. By substituting Eqs. (2)-(4) into Eq. (1), we obtain $$\begin{align} V'_{\rm th}=\,&V'_{\rm th0}+\gamma'(\sqrt{\phi_{\rm s}-V_{\rm bs}} -\sqrt{\phi_{\rm s}})-\frac{\varepsilon_{\rm si} t'_{\rm ox}}{\varepsilon_{\rm ox} \pi L} V_{\rm ds} \\ &-\frac {q g_{0}}{2\varepsilon_{\rm ox}}k'_1\Big[ 1-\exp\Big(-\frac{D}{\tau'}\Big)\Big]{t'_{\rm ox}}^2.~~ \tag {5} \end{align} $$ According to the BSIM3.3 model,[13] the $I$–$V$ equation for the whole region is given as $$\begin{alignat}{1} I'_{\rm ds}=\mu' C'_{\rm ox} \frac{W'}{L} V'_{\rm gst}\Big[1-\frac{A_{\rm bulk} V_{\rm ds}}{2(V'_{\rm gst}+2v_{t})}\Big] V_{\rm ds},~~ \tag {6} \end{alignat} $$ where $\mu'$ is the carrier mobility, $W'$ is the channel width, $A_{\rm bulk}$ is the bulk charge factor, and $V'_{\rm gst}$ is the effective gate overdrive voltage. As illustrated in Fig. 1(b), $W_{\rm main}$, $W_{\rm corner}$, and $W_{\rm STI}$ are channel widths of intrinsic MOS, corner transistor, and STI transistor, respectively.
cpl-33-9-096101-fig2.png
Fig. 2. Sub-circuits of the TID model including a controlled voltage that stands for subthreshold voltage shift, and a controlled current source stands for leakage current from drain to source.
As depicted in Fig. 2, $I'_{\rm ds,CCS}$ is the current of controlled-current-source (CCS), it stands for current of corner and STI, $$\begin{align} I'_{\rm ds,CCS}=I'_{\rm ds,corner}+I'_{\rm ds,STI},~~ \tag {7} \end{align} $$ where $I'_{\rm ds,corner}$ and $I'_{\rm ds,STI}$ are the currents for corner and STI transistors, respectively. Finally, the drain-source current including intrinsic MOS and parasitic transistors can be expressed as $$\begin{align} I_{\rm ds}=I_{\rm ds,main}+I'_{\rm ds,CCS},~~ \tag {8} \end{align} $$ where $I_{\rm ds,main}$ is the intrinsic MOS current from drain to source, and its value is obtained from the commercial model. For the thick gate oxide, traps built up at and near the interface can decrease (or increase for pMOSFET) the threshold voltage to some extent. Thus we use the similar method to construct a controlled-voltage-source (CVS) to model this threshold voltage shift behavior, $$\begin{align} \Delta V_{\rm th}=\frac {q g_{0}}{2\varepsilon_{\rm ox}}k'_2 \Big[1-\exp\Big(-\frac{D}{\tau'}\Big)\Big]{t'_{\rm ox}}^2,~~ \tag {9} \end{align} $$ where $k'_2$ is the scale parameter for the intrinsic transistor. For further discussion, we firstly define $D_{\rm si}=0.58D$ by the conversion factor relationship,[15] where $D_{\rm si}$ is radiation dose in silicon. The structure of the intrinsic MOS, CCS, and CVS is illustrated in Fig. 2. We implement the CCS and CVS with Verilog-A, and combine the sub-circuits into a new SOI model which has the same port name outside. Importantly, the core model is depicted in Fig. 2, based on the standard commercial model without any modification. Designers can treat the TID model as a plugable model that they can use to switch over the commercial model and the TID model conveniently. To validate the proposed model, simulations were carried out with the EDA tool HSPICE. The irradiation experiment was performed at Xinjiang Technical Institute of Physics and Chemistry, Chinese Academy of Sciences. The 0.13 μm SOI CMOS process was used, top silicon and buried oxide thickness are 100 nm and 145 nm, respectively. IO and core devices were irradiated at gate-to-body biases of 3.3 V and 1.2 V, respectively, using $^{60}$Co gamma rays at a dose rate of 125 rad(Si)/s. Doses range from 50 to 200 krad(Si) for the IO device, and from 100 to 1000 krad(Si) for the core device. The same scale of the IO and core devices are chosen to validate the model. Current-voltage measurements are performed with the Keithley 4200 semiconductor parametric analyzer.
Table 1. Summary of the fitting parameters of the CCS and CVS for IO and core devices.
Corner$^{\rm a}$ STI$^{\rm a}$ Front gate$^{\rm a}$
$V'_{\rm th0}$ (V) 4.12/1.14 1.13/0.160
$\gamma'$ (V$^{-0.5}$) 0.398/0.339 11.9/29.1
$t'_{\rm ox}$ (nm) 19.2/5.9 114.8/101.5 6.75/2.44
$k'_{1}$ ($10^4$) 73.7/274 7.18/1.64
$k'_{2}$ ($10^4$) 130/200.0
$\tau'$ ($10^3$ rad(Si)) 56.7/472 383/976 1724/31034
$W'$ (nm) 17.7/8.90 61.8/158.9 150/150
$^{\rm a}$Left/right means IO/core devices, respectively.
Table 2. Errors of model and measurements for the IO/core devices. EF: error function.
IO device Core device
0 50 100 150 200 krad(Si) 0 100 400 700 1000 krad(Si)
$\Delta V_{\rm th}$ (mV) 55.2 34.4 14.8 45.6 17.2 6.64 8.98 12.8 17.6 22.3
$\Delta I_{\rm dlin}$ 2.80% 2.81% 0.700% 1.68% 0.600% 1.03% 0.460% 1.24% 0.720% 0.230%
EF 0.164$^{\rm a}$ 0.0657 0.138 0.264 0.208 0.285 0.281 0.205 0.369 0.313
$^{\rm a}$The accuracy of measurement while $V_{\rm g}$ less than 0.25 V is out of range, the error function at 0 krad(Si) is obtained at $V_{\rm g}$ greater than 0.25 V.
Table 1 lists the fitting parameters of the model, extracted by TIDFit, which is a specific software developed for the TID model extraction. Figures 3 and 4 show a series of transfer characteristic and transconductance curves at $V_{\rm d}=0.1$ V. For the IO device, above 50 krad(Si), the leakage current associated with parasitic field oxide is observed. The same characteristic occurs in 700 krad(Si) for the core device. While the saturation effect in leakage current associated with traps is significant observed in Fig. 3(a).
cpl-33-9-096101-fig3.png
Fig. 3. Transfer characteristic curves at $V_{\rm d}=0.1$ V in logarithmic (left) and linear (right) scales for (a) the IO device and (b) the core device before and after radiation.
cpl-33-9-096101-fig4.png
Fig. 4. The corresponding transconductance characteristics of devices in Fig. 3: (a) IO device, and (b) core device.
Characteristic of subthreshold region such as $V_{\rm th}$ determines $I_{\rm dlin}$ at gate voltage of 3.3 V for the IO device (and 1.2 V for core device). In general, $V_{\rm th}$ can be obtained by the transconductance method,[13] which corresponds to the maximum value in the transconductance curve. From Fig. 4, shift of curves shows the detail of threshold voltage shift $\Delta V_{\rm th}$. For quantitatively validation, we use the least-square function to evaluate the model accuracy $$\begin{align} {\rm Error}=\sqrt{\frac{1}{m}\sum^{m}_{i=1}{\Big(\frac{I_{{\rm sim},i}-I_{{\rm mea},i}}{I_{{\rm mea},i}}\Big)}^2},~~ \tag {10} \end{align} $$ where $I_{{\rm sim},i}$ and $I_{{\rm mea},i}$ mean simulation and measurement, respectively, $m$ is equal to the number of data points, and $V_{\rm th}$, $I_{\rm dlin}$, and error function results are listed in Table 2. From Table 2 it can be seen that the errors of the parameters are less than 5.0%, the error function is less than 0.5, and it quantitatively shows a good agreement of the simulation result with the measurement. In summary, a new compact model has been developed for TID modeling in partially depleted SOI MOSFETs. A method that combines the TID model into a commercial model is obtained. There is no need to modify the commercial model or extra test structure for modeling, which is convenient for quick and accurate modeling. In addition, the exponential approximation is suggested to simplify calculation of trap charge distribution. By simulating the transfer characteristics of the IO and core devices, we quantitatively compare the threshold voltage, saturation current at low voltage bias, and error function for the whole scale. This shows that the simulation results have good agreement with the experimental data. References Challenges in hardening technologies using shallow-trench isolationCompact Modeling of Total Ionizing Dose and Aging Effects in MOS TechnologiesA Concise Numerical TID Radiation Model for <I>n</I>-MOSFET with Nano-Scaled LOCOS Isolation Under Zero Gate BiasIncluding Radiation Effects and Dependencies on Process-Related Variability in Advanced Foundry SPICE Models Using a New Physical Model and Parameter Extraction ApproachModeling of Radiation-Induced Leakage and Low Dose-Rate Effects in Thick Edge Isolation of Modern MOSFETsTotal ionizing dose effect in 0.2μm PDSOI NMOSFETs with shallow trench isolationThe Enhanced Role of Shallow-Trench Isolation in Ionizing Radiation Damage of Narrow Width Devices in 0.2 μm Partially-Depleted Silicon-on-Insulator TechnologyEnhanced Total Ionizing Dose Hardness of Deep Sub-Micron Partially Depleted Silicon-on-Insulator n-Type Metal-Oxide-Semiconductor Field Effect Transistors by Applying Larger Back-Gate Voltage StressRadiation Effects in MOS Oxides
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