⇦Chinese Physics Letters, 2016, Vol. 33, No. 8, Article code 087302⇨ Low-Frequency Noise in Gate Tunable Topological Insulator Nanowire Field Emission Transistor near the Dirac Point * Hao Zhang(张浩)1,2, Zhi-Jun Song(宋志军)2, Jun-Ya Feng(冯军雅)2, Zhong-Qing Ji(姬忠庆)2**, Li Lu(吕力)2 Affiliations 1Department of Physics, Northwest University, Xi'an 710069 2Institute of Physics, Chinese Academy of Sciences, Beijing 100190 Received 26 April 2016 ^*Supported by the National Basic Research Program of China under Grant No 2012CB921703, the National Natural Science Foundation of China under Grant Nos 11174357 and 11574379, and the Strategic Priority Research Program of Chinese Academy of Sciences under Grant No XDB07010300.
^**Corresponding author. Email: zji@iphy.ac.cn Citation Text: Zhang H, Song Z J, Feng J Y, Ji Z Q and Lu L 2016 Chin. Phys. Lett. 33 087302 Abstract Low-frequency flicker noise is usually associated with material defects or imperfection of fabrication procedure. Up to now, there is only very limited knowledge about flicker noise of the topological insulator, whose topologically protected conducting surface is theoretically immune to back scattering. To suppress the bulk conductivity we synthesize antimony doped Bi$_2$Se$_3$ nanowires and conduct transport measurements at cryogenic temperatures. The low-frequency current noise measurement shows that the noise amplitude at the high-drain current regime can be described by Hooge's empirical relationship, while the noise level is significantly lower than that predicted by Hooge's model near the Dirac point. Furthermore, different frequency responses of noise power spectrum density for specific drain currents at the low drain current regime indicate the complex origin of noise sources of topological insulator. DOI:10.1088/0256-307X/33/8/087302 PACS:73.25.+i, 73.63.Nm, 72.70.+m © 2016 Chinese Physics Society Article Text As a new class of quantum materials with insulating bulk states and conducting surface states, topological insulators (TIs)[1-5] are promising function materials for future electronic applications, due to their robust, topologically protected surface states. Since low frequency $1/f$ (flicker) noise of electronic devices is usually associated with material defects or imperfection of fabrication procedure, the level of $1/f$ noise is usually used as the measure of material quality.[6-12] Thus it will be interesting to examine $1/f$ noise for topological insulator devices when their transport is dominated by conductive surface states. Bismuth selenide (Bi$_2$Se$_3$) is one of the most studied three-dimensional topological insulators, due to its relatively large bandgap and the simple band structure with a unique Dirac cone.[13,14] The strong spin–orbit coupling of TIs inverts the valence and conduction bands of bulk electrons and creates the Dirac cone-type surface states at boundaries. The topological surface states of Bi$_2$Se$_3$ have already been verified by angle-resolved photoemission spectroscopy[13,15] and scanning-tunneling microscopy[16,17] methods. However, like all other known 3D topological insulators, Bi$_2$Se$_3$ also suffers from significant bulk conductivity owing to excess charges from Se vacancies.[18-22] A large number of experimental studies have focused on enhancing the surface contribution in total conducting channels by suppressing the bulk conductivity. For example, the efforts of shifting the Fermi level downwards from conduction bands across the Dirac point by using electrical gating have been presented on ultra-thin Bi$_2$Se$_3$ nanoplates,[23-25] eliminating bulk carriers in total conductivity. Another efficient way to reduce the bulk carrier concentration is the introduction of compensation doping. For instance, antimony doping reduces the bulk conductivity significantly and shifts the Fermi level of the bulk states of Bi$_2$Se$_3$ closer to the Dirac point,[26-28] leading to a larger gating response than that with pure Bi$_2$Se$_3$. Some research reported that bulk carriers can be frozen further at a sufficiently low temperature,[9,27,29,30] which is valid for most low-temperature transport experiments performed nowadays. Although all current 3D TIs are still far from true bulk insulators by the Mott criterion, theoretical analysis predicts insulating bulk states in ultra-thin regime due to the band-bending effect.[18] Meanwhile, increasing evidence of surface-dominated conduction, such as Shubnikov-de Haas (SdH) oscillations,[31-36] Aharonov–Bohm (AB) interference,[37-39] are realized on topological insulating nano-plates and nano-ribbons. In this Letter, several methods as mentioned above are used to reduce the bulk conducting contribution in total conductivity. Antimony-doped Bi$_2$Se$_3$ nanowires are synthesized via a vapor–liquid–solid process to reduce the bulk carrier concentration. As a pseudo-one-dimensional nanostructure with naturally larger surface to volume ratio, nanowire provides a better platform for studying surface-related effects, compared with bulk or sheet materials. An additional benefit of nanowire FETs over nano-plate devices is their generally larger gating response due to the deeper electrical field penetration, which makes them more promising from a practical perspective. In experiment, the synthesis of nanowires was carried out with a three-zone tube furnace via a vapor-liquid-solid method based on Ref. [27]. High purity Bi$_2$Se$_3$ powder (Alfa 99.999%) was placed in the middle zone of the quartz tube at the highest temperature of near 530$^{\circ}$. The dopant source of Sb$_2$Se$_3$ (Alfa 99.999%) was placed in the upstream position at a lower temperature. The doping amount can be controlled by adjusting dopant evaporation temperature. The usage of the three-zone tube furnace can achieve more precise temperature control but requires accurate synchronization between the source and dopant zones to evaporate both source and dopant simultaneously. High-purity argon gas flew through the quartz tube to carry the vapor. In the downstream zone at the lowest temperature, Sb-doped Bi$_2$Se$_3$ nanowires were synthesized via the VLS growth mechanism by using pre-deposited 10 nm gold nanoparticles on silicon wafers as catalysts. A representative growth wafer with nanowires/plates of various sizes is demonstrated in Fig. 1(a). The majority of nanowires are 20–80 nm in width and a few micrometers in length. A high resolution TEM analysis in Fig. 1(b) shows that the growth direction of Bi$_2$Se$_3$ is close to [110]. A semi-quantitative EDX analysis in Fig. 1(c) indicates the Sb dopant concentration to be around 14%, which is significantly higher than the value reported in Ref. [27]. The carrier density $3.2\times10^{12}$ cm$^{-2}$ and mobility 7000 cm$^2$/V$\cdot$s were estimated with the Hall measurement on a nano-plate on the same growth substrate.

Fig. 1. Bi$_2$Se$_3$ nanowires synthesized in a horizontal tube furnace via a vapor–liquid–solid process. (a) SEM image of a growth wafer with Sb-doped Bi$_2$Se$_3$ nanowires and plates. (b) HRTEM image of Sb-doped Bi$_2$Se$_3$ nanowires showing that the growth direction is close to 110, and the SAED pattern as the inset. (c) EDX spectra from nanowires of doped Sb, in which the table inset indicates homogeneous dopant distribution of 14 (atomic percentage) Sb. (d) The resistance versus temperature by four-terminal measurement, in which the inset shows the resistance versus temperature from 10 mK to 30 K for another device.

The nanowires were transferred subsequently via a dry deposition method. Specifically, a nanowire growth substrate was placed upside down on top of the Si/SiO$_2$ substrate with predefined alignment marks with gentle pressure applied. After removing the growth substrate, only nanowires of 30–40 nm in width and a few micrometers in length among the remaining nanowires were selected with a microscope and then fabricated to multi-terminal geometry with e-beam lithography and e-beam evaporation. By subtracting the resistance measured with two-terminal configuration to that with three-terminal configuration we can estimate the contact resistance between Pd–Au electrodes and nanowires to be around 100 $\Omega$, which is negligible for transport and noise measurements, as the resistances of most our nanowire devices are two orders higher. The highly p-doped Si beneath the 100 nm SiO$_2$ insulator layer of the substrate functioned as the back gate of nanowire FETs. The resistance-versus-temperature measurements were carried out with a quantum design PPMS from room temperature to 1.8 K (Fig. 1(d)) and with a dilution refrigerator from 30 K to 10 mK (Fig. 1(d) inset for another sample) separately. Unlike devices fabricated with thick films or thick nano-ribbons in Refs. [9,27] in which the sheet resistance of devices saturates at around 100 K due to the freezing of bulk carriers, all our thin nanowire devices show the typical metallic behavior with steady decreasing resistance from room temperature to a low temperature. Below that point the resistance increases sharply as the temperature decreases. A representative 4-terminal resistivity curve as a function of temperature is shown in Fig. 1(d). The tendency of curves coincides with that reported in Refs. [9,27,29] for ultra-thin topological insulator films of less than 10 nm in thickness, indicating the similar transport mechanism at a cryogenic temperature. The radical increase of resistance at a low temperature indicates the strong Anderson localization and the existence of insulating ground state.[30,35]

Fig. 2. (a) The $I$–$V$ characteristics of Sb-doped Bi$_2$Se$_3$ nanowire FET at 4.2 K for different gate voltages. (b) Transfer characteristics of Sb-doped Bi$_2$Se$_3$ nanowire FET. Inset: the schematic diagram of the device and the circuit diagram of tuning chemical potential by back gate.

Both the low-temperature $I$–$V$ characterization and low-frequency current noise measurement were carried out with a home-made liquid helium dip-stick equipped with high-bandwidth semi-rigid coaxial cables. The representative $I$–$V$ characteristics of a device at 4.2 K in Fig. 2(a) show a typical metallic behavior with no sign of current saturation before the device is burning out. The differential resistance measurement in Fig. 2(b) is performed with a normal 4-terminal AC measurement by using lock-in amplifiers. Compared with our pure Bi$_2$Se$_3$ nanowire devices, whose resistance changes less than 5% with 30 V gate voltage applied, Sb-doped Bi$_2$Se$_3$ nanowires have vastly improved gating response. It is easy to tune the Fermi level cross over the Dirac point with only a few volts applied to the back gate, indicating the position of Fermi level to be much closer to the Dirac point, based on the single Dirac cone band diagram as shown in Fig. 2(b). Quantum oscillations, such as SdH oscillations and AB effect, are usually labeled as the signature of surface states in magneto-resistance measurements, although the origin of these signals can also be ascribed to bulk states or trivial surface states. It is worth noting that none of our devices show convincing quantum oscillations on magneto-resistance measurements performed on a dilution refrigerator due to the small cross-section area of our nanowire devices, which leads to a large corresponding period of oscillations beyond the limit of our maximum 6-1-1 magnetic field. This result is consistent with Ref. [27], in which the period of SdH oscillations for Sb-doped Bi$_2$Se$_3$ nano-ribbon becomes larger as the Sb-doping concentration increases, and eventually the SdH oscillations disappear for highly-doped devices.

Fig. 3. (a) Current noise spectral density for different source–drain bias currents at $V_{\rm g}=0$. Inset: schematic diagram of noise measurement. (b) Normalized current noise spectral density for different back-gate voltages at source–drain current $I_{\rm ds}=30$ μA. Inset: integrated noise versus the gate voltage.

The schematic diagram of low frequency noise measurement is shown in the inset of Fig. 3(a). Both bias voltage and back-gate voltage for Sb-doped Bi$_2$Se$_3$ nanowire were generated by a Keithley source measurement unit in series with an RC low-pass filter to minimize the noise contribution from the source meter. Low frequency current noise of the nanowire transistor was measured with a Femto trans-impedance amplifier through a 220 μF low-leakage polypropylene capacitor as a dc blocker. The source–drain current bias was implemented through a 1 M$\Omega$ resistor, which also functioned as a current noise blocker in FET biasing loop to ensure the majority of current noise was injected into the trans-impedance amplifier. The low cut-off frequency of 1 Hz was set by the dc blocking capacitor and the input impedance of Femto amplifier. The converted noise was monitored with a HP89410A spectrum analyzer (dc-10 MHz). The measured current noise spectral density is shown in Fig. 3. It is interesting to note that the noise spectrum curves for specific low drain currents have different frequency responses, as shown in Fig. 3(a). For example, the noise spectrum curve for drain current of 15 μA has significantly higher noise contribution at near 1000 Hz, while at the same frequency the noise spectrum of 20 μA drain current is significant lower. This kind of behavior only happens for relatively low bias currents and is repeatable for every device we measured and in every test facility, including the dilution refrigerator and the liquid helium dip stick. This may indicate the complex origin of low-frequency noise and transport mechanism of topological insulators. For relatively high drain currents, as shown in Fig. 3(b), the low-frequency noise spectrum can be fitted with the empirical Hooge's model of flicker noise,[41,42] $$ S_{I}=\frac{AI^{\gamma}}{f^{\beta}},~~ \tag {1} $$ where $S_{I}$ is the current noise spectral density, $I$ is the source–drain current, $f$ is the frequency, and parameters $\beta$ and $\gamma$ are close to 1 and 2 in ideal Hooge's model. Noise amplitude $A$ is an empirical parameter obtained from fitted curves. The nanowire's source–drain current is set to a relatively high value of 30 μA. From Fig. 3(b), the noise spectral density is in good agreement with $1/f$ behavior with $\beta$ between 0.96 and 1.07 for different gate voltages. The noise amplitude can be written as $A=\alpha_{_{\rm H}} / N$, where $\alpha_{_{\rm H}}$ is the Hooge parameter, and $N$ is the total number of carriers of the device. Based on the carrier density $3.2\times10^{12}$ cm$ ^{-2}$ from the Hall measurement for a nano-plate on the same growth wafer, the total number $N$ can be roughly estimated with the area carrier density multiplied by the area of both top and bottom surfaces with 50 nm in width and 1 μm in length. The Hooge parameter is then extracted as $1.2\times 10^{-3}$, which is comparable with the noise levels reported on graphene and InAs nanowire devices. To compare the noise levels at different gate voltages, we have integrated the noise spectrum over the measurement bandwidth from 10 Hz to 10 kHz to minimize the influence of shape variations of noise spectrum curves. The inset of Fig. 3(b) shows the normalized noise as a function of the back-gate voltage. The total noise reaches the maximum at the Dirac point, showing the same tendency as the nanowire resistance in Fig. 2(b). It is more convenient to rewrite the $1/f$ noise amplitude as the function of gate voltage instead of the function of device resistance, due to the fact that a device biased to higher resistance normally has higher flicker noise. The total carrier number of one-dimensional nanowire can be estimated by $N=C_{\rm g} L|V_{\rm G}-V_{\rm D}|/e$, where $C_{\rm g}$ is the gate capacitance of a nanowire device, $L$ is the length of conducting channel, and $|V_{\rm G}-V_{\rm D}|$ is the deviation of the gate voltage to the Dirac point. In Hooge's model, the noise amplitude $A$ in Eq. (1) can be rewritten as $$ A=\frac{\alpha_{_{\rm H}}}{N}=\frac{\alpha_{_{\rm H}} e}{C_{\rm g} L |V_{\rm G}-V_{\rm D}|}.~~ \tag {2} $$ Two empirical models are normally used to evaluate low frequency noise: (1) McWhorther's model,[8,40] in which flicker noise is originated from the trapping and regrouping of carriers at the surface, having the amplitude $A\propto 1/|V_{\rm G}-V_{\rm D}|^2$; and (2) Hooge's model[8,41,42] $A\propto 1/|V_{\rm G}-V_{\rm D}|$, which attributes the noise as the fluctuation of resistance. From Fig. 4, while the measured data significantly deviate from the McWhorther model (dashed-dotted line), the integrated noise of two samples can be fitted with Hooge's model for gate voltages far away from the Dirac point. Although flicker noise reaches the highest level at the Dirac point, as shown in the inset of Fig. 3(b), the noise level is indeed lower than that predicted by Hooge's model (dotted line in Fig. 4), possibly due to back-scattering-free topological surface states.

Fig. 4. Noise amplitude as a function of voltage deviation to the Dirac point for two samples. The dotted line indicates the fitted line based on Hooge's model and the dashed-dotted line reflects the slope by McWhorther's model.

In conclusion, various means are taken to enhance the surface transport contribution of topological insulators in this work. Compensation antimony doping effectively pulls the Fermi level close to the Dirac point, leading to significantly reduced carrier concentration and greatly improved gating response. The Fermi level of Sb-doped Bi$_2$Se$_3$ nanowire can be easily tuned across the Dirac point with only a few volts applied to even relatively weakly coupled back-gate. The differential resistance of TI nanowires as a function of temperature shows the typical metallic behavior from room temperature to a specific low temperature and then increases sharply. This behavior is in good agreement with the results from ultra-thin TI films or nano-ribbons. Low frequency current noise of Sb-doped Bi$_2$Se$_3$ nanowire FET can be modeled by Hooge's empirical equation. The level of noise, which is characterized by the Hooge parameter, is comparable with the reported values of graphene and InAs nanowire devices. At the Dirac point, the noise level reaches the maximum but is much lower than that predicted by Hooge's model. This promising result may shed some light on designing low-noise electronics with topological insulators in the future. References The birth of topological insulatorsColloquium : Topological insulators

Z_{2}

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{Bi}_{2} {Se}_{3}

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{Bi}_{2} {Se}_{3}

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{Bi}_{2} {Se}_{3}

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{Bi}_{2} {Se}_{3}

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_{2}

_{3}

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{Bi}_{2} {Se}_{3}

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\frac{1}{f}

noise1/f noise1/f noise sources

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