⇦Chinese Physics Letters, 2016, Vol. 33, No. 5, Article code 058501 Influence of Post-Annealing on Electrical Characteristics of Thin-Film Transistors with Atomic-Layer-Deposited ZnO-Channel/Al$_{2}$O$_{3}$-Dielectric * You-Hang Wang(王有航), Qian Ma(马倩), Li-Li Zheng(郑丽丽), Wen-Jun Liu(刘文军), Shi-Jin Ding(丁士进)**, Hong-Liang Lu(卢红亮), Wei Zhang(张卫) Affiliations State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433 Received 17 November 2015 *Supported by the National Natural Science Foundation of China under Grant Nos 61474027 and 61376008.
**Corresponding author. Email: sjding@fudan.edu.cn Citation Text: Wang Y H, Ma Q, Zheng L L, Liu W J and Ding S J et al 2016 Chin. Phys. Lett. 33 058501 Abstract High-performance thin-film transistors (TFTs) with a low thermal budget are highly desired for flexible electronic applications. In this work, the TFTs with atomic layer deposited ZnO-channel/Al$_{2}$O$_{3}$-dielectric are fabricated under the maximum process temperature of 200$^{\circ}\!$C. First, we investigate the effect of post-annealing environment such as N$_{2}$, H$_{2}$-N$_{2}$ (4%) and O$_{2}$ on the device performance, revealing that O$_{2}$ annealing can greatly enhance the device performance. Further, we compare the influences of annealing temperature and time on the device performance. It is found that long annealing at 200$^{\circ}\!$C is equivalent to and even outperforms short annealing at 300$^{\circ}\!$C. Excellent electrical characteristics of the TFTs are demonstrated after O$_{2}$ annealing at 200$^{\circ}\!$C for 35 min, including a low off-current of $2.3\times10^{-13}$ A, a small sub-threshold swing of 245 mV/dec, a large on/off current ratio of 7.6$\times$10$^{8}$, and a high electron effective mobility of 22.1 cm$^{2}$/V$\cdot$s. Under negative gate bias stress at $-$10 V, the above devices show better electrical stabilities than those post-annealed at 300$^{\circ}\!$C. Thus the fabricated high-performance ZnO TFT with a low thermal budget is very promising for flexible electronic applications. DOI:10.1088/0256-307X/33/5/058501 PACS:85.30.Tv, 85.30.De, 81.15.Gh © 2016 Chinese Physics Society Article Text Recently, flexible electronics have received increasing attention due to the fact that they are lightweight, thin, and bendable. As a key component for flexible electronic applications, thin-film transistors (TFTs) must be fabricated under a thermal budget as low as possible while maintaining high device performance. Although organic TFTs are very suitable for the flexible manufacture due to their low processing temperature, the low carrier mobility ($ < $1 cm$^{2}$/V$\cdot$s) and ordinary reliability overshadow their device performance attributes.[1,2] Compared with organic semiconductors, ZnO is also regarded as an excellent candidate for flexible electronic application due to its high electron mobility, low processing temperature, high transparency for visual light and excellent environmental stability.[3,4] Among various preparation methods of ZnO films, the atomic-layer-deposition (ALD) technique can ensure excellent thickness uniformity, nearly stoichiometric composition and relatively low deposition temperature. These make it very attractive for the TFT fabrication on a flexible substrate. However, the ALD ZnO films generally have a very high carrier concentration, thus the ZnO-channel of TFT is conductive even in the absence of an applied gate voltage.[5] This makes the ZnO TFT unable to work in a normal mode. To solve this issue, some strategies have been attempted to reduce the carrier concentration in the ZnO channel to improve the device performance.[6-10] Unfortunately, they either require a high annealing temperature (400$^{\circ}\!$C),[3,10] or improve the device performance slightly.[6-9] Therefore, it is imperative to explore low temperature fabrication of high-performance ZnO TFTs for flexible electronic applications. In this Letter, the TFTs with ALD ZnO-channel/Al$_{2}$O$_{3}$ -dielectric were fabricated under the maximum processing temperature of 200$^{\circ}\!$C. In particular, O$_{2}$ post-annealing at 200$^{\circ}\!$C was investigated intensively. As a result, excellent device performance has been achieved, such as a large on/off current ratio, a high electron effective mobility, a small sub-threshold swing and good electrical stabilities under negative gate bias stressing (NGBS). A low resistivity p-type (100) silicon substrate was used as the back gate electrode of TFTs. After standard RCA cleaning, a 50-nm Al$_{2}$O$_{3}$-dielectric layer and a 37-nm ZnO active layer were deposited in turn by ALD at 200$^{\circ}\!$C without breaking the vacuum. Herein, the precursors for ALD Al$_{2}$O$_{3}$ and ZnO films were Al(CH$_{3})_{3}$/H$_{2}$O and Zn(C$_{2}$H$_{5})_{2}$/H$_{2}$O, respectively. Subsequently, the active layer of ZnO was defined by photolithography, and was formed by wet etching with diluted HCl solution. Then, the source and drain contacts of the 100-nm Mo layer were formed by sputtering and a lift-off process. After that, the device was first annealed in N$_{2}$, N$_{2}$-H$_{2}$ (4%) and O$_{2}$, respectively, to improve and optimize its performance. Then, the environment of O$_{2}$ was selected as a perfect annealing environment, and the influences of annealing temperature and time on the electrical characteristics of the device were studied comprehensively, especially at the temperature as low as 200$^{\circ}\!$C. The thicknesses of the deposited ZnO and Al$_{2}$O$_{3}$ films were determined by an ellipsometer (Sopra GES-SE, France). The texture of the ZnO film was characterized with x-ray diffraction (XRD). The electrical characteristics of the TFTs were measured with a semiconductor device analyzer (B1500A, Agilent Technologies, Japan) at room temperature in a dark box.
cpl-33-5-058501-fig1.png
Fig. 1. Schematic diagram (a) and optical top view (b) of the fabricated TFT device.
cpl-33-5-058501-fig2.png
Fig. 2. Transfer characteristics of the ZnO TFTs: (a) annealed at 300$^{\circ}\!$C for 5 min in N$_{2}$, N$_{2}$-H$_{2}$(4%), and O$_{2}$, respectively, (b) annealed at different temperatures for 5 min in O$_{2}$.
Figure 1 shows the schematic structure and top view of the fabricated TFT device. It is indicated that the Mo electrodes and the ZnO channel overlap, thus ensuring sufficient contact between the source/drain electrode and the channel. To find out the effect of annealing environment on the electrical characteristics of the TFTs, the fabricated devices were first annealed in N$_{2}$, N$_{2}$-H$_{2}$(4%) and O$_{2}$, respectively, at 300$^{\circ}\!$C for 5 min. As shown in Fig. 2(a), the annealing in O$_{2}$ can result in the best transfer characteristics of the device compared with the annealing in N$_{2}$ or N$_{2}$-H$_{2}$(4%). Therefore, the influence of annealing temperature on the transfer characteristics of the ZnO TFTs was further studied in the environment of O$_{2}$ under a constant annealing time of 5 min, as shown in Fig. 2(b). It is found that the device does not exhibit a normal $I_{\rm d}$–$V_{\rm g}$ characteristic of the TFT until the annealing temperature increases to 250$^{\circ}\!$C. This can be understood as follows: O$_{2}$ annealing at higher temperatures can effectively passivate oxygen vacancies supplying free electrons in the ZnO channel,[11] hence reducing the carrier concentration in the ZnO film.[3] Further, as the annealing temperature rises from 250 to 350$^{\circ}\!$C, the off-current of the device increases by around one order of magnitude, and the on-current also decreases evidently. As Janotti et al. reported, Zn atoms in ZnO could diffuse into Al$_{2}$O$_{3}$ at higher annealing temperatures of $\ge$300$^{\circ}\!$C,[12] thus resulting in the formation of a Zn-doped alumina (ZAO) layer at the Al$_{2}$O$_{3}$/ZnO interface. However, the ZAO layer contains numerous charge trapping centers,[13] which likely provide extra leakage paths between source and drain, and enhance carriers trapping as well. This is also confirmed by the drop of effective mobility from 14.2 to 6.8 cm$^{2}$/V$\cdot$s with increasing the annealing temperature from 250 to 350$^{\circ}\!$C.
cpl-33-5-058501-fig3.png
Fig. 3. XRD patterns of the as-deposited ZnO film (40 nm) and those annealed at different temperatures for different times.
Figure 3 shows the XRD patterns of the as-deposited ZnO film and those annealed under different conditions. All the ZnO films show a hexagonal wurtzite structure associated with the (100), (002), and (101) diffraction peaks. Based on the full width at half maximum (FWHM) of the preferential (002) peak, the average grain size was estimated by the Sherrer equation $$ D=\frac{0.9\lambda }{B\cos \theta}, $$ where $\lambda$, $B$ and $\theta$ denote the x-ray wavelength, the FWHM of the (002) peak, and the corresponding Bragg diffraction angle, respectively. Therefore, the mean grain size of the as-deposited ZnO film is 18.54 nm, and those for the films annealed at 200$^{\circ}\!$C, 300$^{\circ}\!$C and 400$^{\circ}\!$C for 20 min are 20.51, 22.95 and 28.36 nm, respectively. This indicates that the annealing temperature has a significant influence on the crystallization of the ZnO film, which should be related to the annealing temperature-dependent performance of the device. However, for the annealing at 200$^{\circ}\!$C, the crystallization of the ZnO film is slightly dependent on annealing time. For example, when the annealing time increases from 20 to 40 min, the average grain size only increases by 0.45 nm. Considering that the passivation of oxygen vacancies in ZnO could be related to annealing time in addition to the annealing temperature, we thus attempted to extend annealing time at 200$^{\circ}\!$C. As shown in Fig. 4(a), when the cumulative annealing time increases to 10 min, the electrical performance of the ZnO TFT is improved significantly in comparison with 5 min annealing time. Further, as the cumulative annealing time increases gradually from 15 min to 40 min, the $I_{\rm d}$–$V_{\rm g}$ curves exhibit a small change, and the corresponding electrical parameters are listed in Table 1. In terms of sub-threshold swing $S$, annealing for 35 min causes a minimum $S$ of 245 mV/dec while maintaining other superior characteristics, i.e., $\mu_{\rm ef}=22.1$ cm$^{2}$/Vs, $I_{\rm on}/I_{\rm off}=7.6\times10^{8}$, and maximum $I_{\rm off}=2.3\times10^{-13}$ A. From $S$, the maximum density of interface states at the ZnO/Al$_{2}$O$_{3}$ interface can be deduced as $D_{\rm it}=[\frac{S \log e}{kT/q}-1]$, where $q$, $k$, and $T$ are the unit electron charge, Boltzmann's constant, and absolute temperature, respectively. Based on the extracted $S$ value and the unit area capacitance of the Al$_{2}$O$_{3}$ layer, $D_{\rm it}$ of the device annealed at 200$^{\circ}\!$C for 35 min is calculated to be 2.98$\times$10$^{12}$ eV$^{-1}$cm$^{-2}$, and $D_{\rm it}$ for the device annealed at 200$^{\circ}\!$C for 10 min is 7.25$\times$10$^{12}$ eV$^{-1}$cm$^{-2}$. This indicates that increasing annealing time at 200$^{\circ}\!$C can reduce the interface states, which is mainly ascribed to effective passivation of oxygen vacancies at the interface of ZnO/Al$_{2}$O$_{3}$,[14] rather than the change of crystallization in the ZnO channel. For comparison, Fig. 4(b) shows the transfer characteristics of the ZnO TFT as a function of the annealing time at a higher temperature of 300$^{\circ}\!$C. Different from the annealing at 200$^{\circ}\!$C, 5 min annealing at 300$^{\circ}\!$C can result in good performance of the device. As the annealing time increases up to 20 min or above, the $I_{\rm d}$–$V_{\rm g}$ curve does not exhibit evident variation. This indicates that the annealing at a higher temperature can rapidly passivate oxygen vacancies in the ZnO channel. Table 2 compares the electrical parameters of our device annealed at 200$^{\circ}\!$C and others. It is found that our device demonstrates much better electrical characteristics than others, even compared with those annealed at higher temperatures.
Table 1. Major electrical parameters of the ZnO TFTs annealed at 200$^{\circ}\!$C for different times in O$_{2}$.
Annealing time (min) Max $I_{\rm off}$ (A) $\mu_{\rm ef}$ (cm$^{2}$/V$\cdot $s) $I_{\rm on}/I_{\rm off}$ $V_{\rm th}$ (V) $S$ (mV/dec)
10 9.3$\times$10$^{-14}$ 23.9 1.6$\times$10$^{9}$ 2.48 510
15 1.3$\times$10$^{-13}$ 19.5 1.8$\times$10$^{9}$ 3.73 410
20 1.4$\times$10$^{-13}$ 19.6 1.01$\times$10$^{9}$ 4.51 360
25 1.7$\times$10$^{-13}$ 20.7 1.03$\times$10$^{9}$ 4.64 354
30 1.9$\times$10$^{-13}$ 20.5 7.8$\times$10$^{8}$ 4.25 347
35 2.3$\times$10$^{-13}$ 22.1 7.6$\times$10$^{8}$ 4.89 245
40 3.0$\times$10$^{-13}$ 21.6 6.1$\times$10$^{8}$ 4.90 264
Table 2. Comparison of major electrical parameters between our device and other ZnO TFT devices.
$T_{\max}$($^{\circ}\!$C) $I_{\rm on}/I_{\rm off}$ $\mu_{\rm ef}$ (cm$^{2}$/V$\cdot$s) $V_{\rm th}$ (V) $S$ (mV/dec)
200 7.6$\times$10$^{8}$ 22.1 4.89 245 This work
90 2.43$\times$10$^{6}$ 0.13 13.1 1210 Ref. [7]
140 2.2$\times$10$^{6}$ 1.786 11.43 710 Ref. [8]
150 9.5$\times$10$^{7}$ 6.7 4.1 670 Ref. [6]
200 $\sim 10^{7}$ 6.3 $-7.5$ 420 Ref. [5]
300 5$\times$10$^{7}$ 3.9 1350 Ref. [9]
400 $>10^{7}$ 21.3 4.9 390 Ref. [2]
It is known that the amount of time that a typical TFT spends under NGBS is approximately 500 times that spent under a positive gate bias in the active matrix liquid crystal display applications.[15] Therefore, NGBS is more important than positive gate bias stress. To compare the electrical instabilities of the ZnO TFTs annealed under different conditions, the devices were subjected to a negative gate bias stress (i.e., $V_{\rm G}=-10$ V and $V_{\rm DS}$ grounded) for different times at room temperature. Figure 5 shows the dependences of threshold voltage shift ($\Delta V_{\rm th}$) and sub-threshold swing variation ($\Delta S$) of the TFTs on stress time under different annealing conditions. Regarding the devices annealed at 200$^{\circ}\!$C for 35 min, as the stress time increases from 500 to 2000 s, $\Delta V_{\rm th}$ shifts approximately from $-$0.01 to $-$0.11 V and $\Delta S$ increases from 0.04 to 0.07 V/dec. However, for the devices annealed at 300$^{\circ}\!$C for 5 min, $\Delta V_{\rm th}$ moves from $-$0.05 V to $-$0.17 V and $\Delta S$ rises from 0.04 to 0.12 V/dec. These results reveal that the annealing at 200$^{\circ}\!$C for 35 min can produce better stability under NGBS than that at 300$^{\circ}\!$C for 5 min. The shift of $V_{\rm th}$ toward negative bias under NGBS should result from accumulation of positive ionized oxygen vacancies at the ZnO/Al$_{2}$O$_{3}$ interface,[16,17] which is also accompanied by degradation of $S$. To sum up, long annealing at 200$^{\circ}\!$C is equivalent to and even better than short annealing at 300$^{\circ}\!$C.
cpl-33-5-058501-fig4.png
Fig. 4. Transfer characteristics of the ZnO TFTs as a function of cumulative annealing time: (a) at 200$^{\circ}\!$C in O$_{2}$, (b) at 300$^{\circ}\!$C in O$_{2}$.
cpl-33-5-058501-fig5.png
Fig. 5. Dependences of $\Delta V_{\rm th}$ and $\Delta S$ on stress time under negative gate bias stressing ($V_{\rm G}=-10$ V) for the devices: (a) annealed at 200$^{\circ}\!$C for 35 min, (b) annealed at 300$^{\circ}\!$C for 5 min.
In conclusion, the TFTs with ALD ZnO-channel/Al$_{2}$O$_{3}$-dielectric have been fabricated under the maximum thermal budget of 200$^{\circ}\!$C. By post-annealing in O$_{2}$ at 200$^{\circ}\!$C for 35 min, excellent electrical characteristics are achieved, including a small sub-threshold swing of 245 mV/dec, a high on/off current ratio of $7.6\times10^{8}$, and a high electron effective mobility of 22.1 cm$^{2}$/V$\cdot$s. In particular, superior electrical stabilities under NGBS are demonstrated in comparison with the device annealed at 300$^{\circ}\!$C. The current ZnO TFT with high-performance and a low thermal budget is very promising for flexible electronic applications. References Organic Thin Film Transistors for Large Area ElectronicsThe Theoretical Electrical Characteristics of Organic Thin Film Transistors Based on Capacitance ModulationMobility Enhancement and OFF Current Suppression in Atomic-Layer-Deposited ZnO Thin-Film Transistors by Post Annealing in O 2Stable ZnO thin film transistors by fast open air atomic layer depositionHigh-performance ZnO thin-film transistor fabricated by atomic layer depositionHigh performance thin film transistor with low temperature atomic layer deposition nitrogen-doped ZnOCharacteristics of the ZnO thin film transistor by atomic layer deposition at various temperaturesInvestigation of the effects of interface carrier concentration on ZnO thin film transistors fabricated by atomic layer depositionAtomic-layer-deposited ZnO thin-film transistors with various gate dielectricsMechanism for wettability alteration of ZnO nanorod arrays via thermal annealing in vacuum and airFundamentals of zinc oxide as a semiconductor${\rm Al}_{2}{\rm O}_{3}$ Charge Storage Medium for Light-Erasable In–Ga–Zn–O TFT Memory]]>The Effect of Oxygen Partial Pressure during Active Layer Deposition on Bias Stability of a-InGaZnO TFTsThe effect of moisture on the photon-enhanced negative bias thermal instability in Ga–In–Zn–O thin film transistorsComparison of structural and electrical properties of Lu2O3 and Lu2TiO5 gate dielectrics for α-InGaZnO thin-film transistors
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