Temperature-Dependent Effect of Near-Interface Traps on SiC MOS Capacitance

A two-dimensional electrical SiC MOS interface model including interface and near-interface traps is established based on the relevant tunneling and interface Shockley–Read–Hall model. The consistency between simulation results and measured data in the different temperatures shows that this interface model can accurately describe the capture and emission performance for near-interface oxide traps, and can well explain the hysteresis-voltage response with increasing temperature, which is intensified by the interaction between deep oxide traps and shallow oxide traps. This also indicates that the near-interface traps result in an increase of threshold-voltage shift in SiC MOSFET with increasing temperature.