Positive Bias Temperature Instability Degradation of Buried InGaAs Channel nMOSFETs with InGaP Barrier Layer and Al_2O_3 Dielectric

Positive bias temperature instability stress induced interface trap density in a buried InGaAs channel metal-oxide-semiconductor field-effect transistor with a InGaP barrier layer and Al_2O_3 dielectric is investigated. Well behaved split C–V characteristics with small capacitance frequency dispersion are confirmed after the insertion of the InGaP barrier layer. The direct-current I_\rm d–V_\rm g measurements show both degradations of positive gate voltage shift and sub-threshold swing in the sub-threshold region, and degradation of positive \Delta V_\rm g in the on-current region. The I_\rm d–V_\rm g degradation during the positive bias temperature instability tests is mainly contributed by the generation of near interface acceptor traps under stress. Specifically, the stress induced acceptor traps contain both permanent and recoverable traps. Compared with surface channel InGaAs devices, stress induced recoverable donor traps are negligible in the buried channel ones.