Impact of Band-Engineering to Performance of High-k Multilayer Based Charge Trapping Memory

Impact of band-engineering to the performance of charge trapping memory with HfO₂/Ta₂O₅/HfO₂ (HTH) as the charge trapping layer is investigated. Compared with devices with the same total HfO₂ thickness, structures with Ta₂O₅ closer to substrates show larger program/erase window, because the 2nd HfO₂ (next to blocking oxide) serving as part of blocking oxide reduces the current tunneling out of/in the charge trapping layer during program and erase. Moreover, trapped charge centroid is modulated and contributed more to the flat-band voltage shift. Further experiments prove that devices with a thicker 2nd HfO₂ layer exhibit larger saturate flat-band shift in both program and erase operation. The optimized device achieves a 7 V memory window and good reliability characteristics.