An FPGA-Based Pulse Pile-up Rejection Technique for Photon Counting Imaging Detectors

A novel FPGA-based pulse pile-up rejection method for single photon imaging detectors is reported. The method is easy to implement in FPGAs for real-time data processing. The rejection principle and entire design are introduced in detail. The photon counting imaging detector comprises a micro-channel plate (MCP) stack, and a wedge and strip anode (WSA). The resolution mask pattern in front of the MCP can be reconstructed after data processing in the FPGA. For high count rates, the rejection design can effectively reduce the impact of the pulse pile-up on the image. The resolution can reach up to 140 μm. The pulse pile-up rejection design can also be applied to high-energy physics and particle detection.