Hot-Carrier Stress Effects on GIDL and SILC in 90nm LDD-MOSFET with Ultra-Thin Gate Oxide

Hot-carrier degradation for 90nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4nm) gate oxide is investigated under the low gate voltage stress (LGVS) and peak substrate current (I_sub,max) stress. It is found that the degradation of device parameters exhibits saturating time dependence under the two stresses. We concentrate on the effect of these two stresses on gate-induced-drain leakage (GIDL) current and stress induced leakage current (SILC). The characteristics of the GIDL current are used to analyse the damage generated in the gate-to-LDD region during the two stresses. However, the damage generated during the LGVS shows different characteristics from that during I_sub,max stress. SILC is also investigated under the two stresses. It is found experimentally that there is a linear correlation between the degradation of SILC and that of threshold voltage during the two stresses. It is concluded that the mechanism of SILC is due to the combined effect of oxide charge trapping and interface traps for the ultra-short gate length and ultra-thin gate oxide LDD NMOSFETs under the two stresses.