A Ferroelectric Domain-Wall Transistor

Yang-Jun Ou(欧阳俊), Jie Sun(孙杰), Yi-Ming Li(李一鸣), and An-Quan Jiang(江安全)$^{\hyperlink{s}{*}}$

doi:10.1088/0256-307X/40/3/038501

⇦Chinese Physics Letters, 2023, Vol. 40, No. 3, Article code 038501⇨ A Ferroelectric Domain-Wall Transistor Yang-Jun Ou (欧阳俊), Jie Sun (孙杰), Yi-Ming Li (李一鸣), and An-Quan Jiang (江安全)* Affiliations State Key Laboratory of ASIC & System, School of Microelectronics, Fudan University, Shanghai 200433, China Received 20 December 2022; accepted manuscript online 8 February 2023; published online 18 February 2023 ^*Corresponding author. Email: aqjiang@fudan.edu.cn Citation Text: Ou Y J, Sun J, Li Y M et al. 2023 Chin. Phys. Lett. 40 038501 Abstract On the basis of novel properties of ferroelectric conducting domain walls, the domain wall nanoelectronics emerges and provides a brand-new dimension for the development of high-density, high-speed and energy-efficient nanodevices. For in-memory computing, three-terminal devices with both logic and memory functions such as transistors purely based on ferroelectric domain walls are urgently required. Here, a prototype ferroelectric domain-wall transistor with a well-designed coplanar electrode geometry is demonstrated on epitaxial BiFeO$_{3}$ thin films. For the logic function, the current switching between on/off states of the transistor depends on the creation or elimination of conducting domain walls between drain and source electrodes. For the data storage, the transistor can maintain nonvolatile on/off states after the write/erase operations, providing an innovative approach for the development of the domain wall nanoelectronics.

DOI:10.1088/0256-307X/40/3/038501 © 2023 Chinese Physics Society Article Text In recent years, downscaling of complementary metal-oxide-semiconductor devices has become progressively challenging because of the quantum effects,[1] and it is necessary to pursue another way to shrink the nanodevices. Ferroelectric domain wall (DW), a type of quasi-two-dimension interlayer between two ferroelectric domains with different orientations, has attracted great interest due to its novel physical properties including high conductivity different from its bulk counterpart,[2-5] enhanced photovoltaic effect,[6-8] strong magnetoresistance,[9-11] and unusual net magnetic moment.[12] Beneficial from atomic level feature sizes, ferroelectric DWs have the potential to be applied to ultrahigh-density memristors,[13-15] transistors,[16-18] sensors,[19,20] waveguides,[21] and rectifiers.[22,23] The principles of high conductivity of DWs are mainly discussed in relation to the decrease in the bandgap[2,3] and the defects accumulation[24,25] at the domain wall regions. Bismuth ferrite (BiFeO$_{3}$, BFO) is one of typical multiferroics with the coexistence of G-type antiferromagnetism and ferroelectricity at room temperature. It possesses a large spontaneous ferroelectric polarization along $\langle 111 \rangle $ directions and a high Curie temperature ($T_{\rm C} \sim 1103$ K).[26] A BFO thin film can be featured by eight possible ferroelectric polarization orientations in the formation of DWs in three possible angles (180$^{\circ}$, 109$^{\circ}$, and 71$^{\circ}$) under application of an external electric field,[27] which provides a good platform for understanding of intrinsic conduction mechanisms and exploring new nanodevices based on DWs. In this work, three-terminal ferroelectric domain-wall (FEDW) transistors were fabricated on the surface of an epitaxial BFO thin film. Their on/off current states can be controlled by the gate voltage similar to conventional Si-based field-effect transistors (FETs). The conducting channels formed at an on state between drain and source electrodes are nonvolatile, which enable various logic operations for in-memory computing. Device Fabrication. The BFO thin film was deposited on a high-quality (110)-oriented SrTiO$_{3}$ (STO) substrate by pulsed laser deposition (PLD) using a KrF excimer laser. The substrate temperature was 580 ℃ and the oxygen pressure was 10 Pa. The distance between the substrate and the BFO ceramic target (with Bi element excess of 10%) was 4.5 cm. The laser pulse energy was 300 mJ with a pulse frequency of 6 Hz. The typical film growth rate was $\sim$ 1 nm/min. After the growth of BFO, a 30-nm-thick platinum (Pt) layer was deposited on the surface of the BFO thin film by physical vapor deposition (PVD-75, Kurt J. Lesker) at 300 ℃. The platinum layer was patterned and etched into well-designed geometries using electron-beam lithography (EBL; JEOL 6300FS) and reactive ion etching (RIE-10NR, Samco). The sizes of all transistors were checked using a scanning electron microscope (SEM; Sigma HD, Zeiss). Microstructural and Electrical Characterizations. The epitaxial structure of the BFO thin film was analyzed by x-ray diffraction (XRD; D8-Advance, Bruker) using the Cu $K\alpha$ radiation. The topographic images of the BFO thin film were obtained using an atomic force microscope (AFM; Icon, Bruker). The ferroelectric domain patterns were captured by a piezoresponse force microscope (PFM; Icon, Bruker) using a Pt/Ir-coated silicon tip with a radius of $\sim$ $20$ nm at an AC amplitude of 2.5 V and a frequency of 220 kHz. All electrical measurements were performed using a semiconductor analyzer (Agilent, B1500). All current-voltage curves were obtained in voltage sweeping mode. The endurance characteristic was measured in voltage list sweep mode where a long array of output voltages can be defined. The retention characteristic was measured in voltage-time sampling mode. Results and Discussion. High-quality epitaxial BFO thin films were grown on (110) STO substrates by PLD. Such as-grown films have two preferred polarization variants whose in-plane components are both along [001] direction,[28,29] which is beneficial for the topotactic control of DWs within our devices. Figure 1(a) shows the topography of the BFO thin film which is featured by stripe-like texture along the [001] direction. Its rms roughness is $\sim$ 1.46 nm. Figure 1(b) displays its XRD pattern showing the (110) orientation of the BFO thin film. After the growth of BFO film, the thin Pt electrode layer was grown on the surface of the BFO film by PVD and was patterned into gate (G), drain (D) and source (S) electrodes using EBL and RIE, as shown in Fig. 1(c). The interelectrode spacing between each electrode pair is a few hundreds of nanometers that is wide enough to capture PFM images of the switched domains within our devices. Unless specified otherwise, all the FEDW transistors presented in this work have the same geometric parameters as shown in Fig. 1(c). The G–D and G–S electrode pairs are aligned along the [001] direction, in contrast to the D–S electrode pairs along the [$\bar{1}$10] direction. Figure 1(d) shows the schematic of two preferred polarization variants ($P_{1}^{-}/P_{2}^{-}$) in as-grown (110)-oriented BFO films, whose out-of-plane (OP) components both point to the substrate while in-plane (IP) components parallel to the [001] direction. This polarization preference guarantees the appearances of IP polarization rotation within the G–D and G–S electrode pairs under applied electric fields.

Fig. 1. (a) AFM image of the BFO/STO(110) thin film. (b) XRD pattern of the BFO/STO(110). (c) SEM image of an FEDW transistor. (d) Schematic of a BFO unit cell with two preferred polarization variants $P_{1}^{-}$ and $P_{2}^{-}$ separated by 71$^{\circ}$ within as-grown (110)-oriented BFO thin films.

Fig. 2. (a)–(d) IP (left panels) and OP (middle panels) PFM images, and the corresponding device schematics (right panels) after different poling voltages. All PFM measurements were performed in the order from top to bottom. Scale bars: 200 nm.

Figures 2(a)–2(d) present IP (left panels) and OP (middle panels) PFM images and schematics (right panels) of domain structures and on/off states of the devices after different applied poling voltages. The voltages applied to G, D, and S are represented by $V_{\rm g}$, $V_{\rm d}$, and $V_{\rm s}$, respectively. The cantilever of PFM was oriented along the [$\bar{1}$10] direction so that $P_{1}^{-}$ and $P_{2}^{-}$ [Fig. 1(d)] can be distinguished. As shown in Fig. 2(a), the same contrast in both IP and OP PFM phase images indicates the pristine monodomain ($P_{2}^{-}$) within the device. The domain between G and D can be switched to the $P_{1}^{-}$ variant after application of $V_{\rm g}=+$15 V, $V_{\rm d} = 0$ V and $V_{\rm s}$ floating, confirmed by the yellow-black contrast in Fig. 2(b). The switched domain can be widened to bridge S and D when $V_{\rm s}$ changes from floating to 0 V, as shown in Fig. 2(c). Figure 2(d) shows that all switched domains can be erased when $V_{\rm g} = -15$ V and $V_{\rm d}=V_{\rm s} = 0$ V. Note that the OP polarization component remains unchanged during each switching process, proving that only $P_{1}^{-}$ and $P_{2}^{-}$ variants are involved. It can be seen that the domain among G, D, and S can be divided into the left and right parts that can be switched by the applied bias over G–D or G–S electrode pair, respectively. When both the domains within the two parts are switched into the $P_{1}^{-}$ variant, a conducting DW bridging D and S is formed [Fig. 2(c); the gap framed by the red dashed-line square near S is due to poor polarization retention], which turns on the FEDW transistor. When either or both of them remain or reverse into their pristine orientations ($P_{2}^{-}$), the transistor turns off due to lack of a conducting channel between D and S [Figs. 2(b) and 2(d)].

Fig. 3. Electrical characteristics of the FEDW transistor. (a) $I$–$V$ curves of G–D, G–S and D–S electrode pairs. [(b), (c)] $I_{\rm d}-V_{\rm g}$ and extracted $I_{\rm ds}-V_{\rm g}$ transfer curves ($V_{\rm d} = 0$ V) under various applied $V_{\rm s}$. [(d), (e)] $I_{\rm s}-V_{\rm g}$ and extracted $I_{\rm ds}-V_{\rm g}$ transfer curves ($V_{\rm s} = 0$ V) under various applied $V_{\rm d}$. (f) Extracted $I_{\rm ds}$–$V_{\rm s}$ curves ($V_{\rm d} = 0$ V) under various applied $V_{\rm g}$.

For the convenience of the discussion, currents flowing through D/S are represented by $I_{\rm d}/I_{\rm s}$ and are positive/negative when they flow from/into electrodes, respectively. Figure 3(a) shows the current–voltage ($I$–$V$) curves of each electrode pair (i.e., G–D, G–S and D–S). The $I$–$V$ curves of G–D and G–S pairs are hysteretic, which is in consistence with previous observations.[30] The current jumps occur during the forward sweep of $V_{\rm g}$ from $-15$ V to $+$15 V because of the formation of DWs when $V_{\rm g}$ is larger than a coercive voltage ($V_{\rm c}$). In contrast, the $I_{\rm ds}$–$V_{\rm ds}$ curve shows that $I_{\rm ds}$ is always off when $V_{\rm g}$ is floating, where $I_{\rm ds}$ refers to the current flowing from D to S and $V_{\rm ds}=V_{\rm d}-V_{\rm s}$. It can be seen that $V_{\rm g}$ plays a key role in switching domains within the devices. Figure 3(b) shows the hysteretic $I_{\rm d}$–$V_{\rm g}$ curves under different applied $V_{\rm s}$ when $V_{\rm d} = 0$ V. When $V_{\rm s} = 0$ V, $I_{\rm d}$ turns on at $V_{\rm g}=+$8 V and is negative; when $V_{\rm s}$ decreases below $-3$ V, $I_{\rm d}$ becomes positive during the backward sweep of $V_{\rm g}$ from $+$15 V to $-15$ V because of the contribution of the current flowing from D to S, i.e., $I_{\rm d}=I_{\rm dg}+ I_{\rm ds}$, where $I_{\rm dg}$ refers to the current flowing from D to G and is equal to $I_{\rm d}$ when $V_{\rm ds} = 0$ V. After subtracting $I_{\rm dg}$ from $I_{\rm d}$, we derived $I_{\rm ds}$–$V_{\rm g}$ curves, as shown in Fig. 3(c). All sweeping curves show anticlockwise hysteresis in which $I_{\rm ds}$ jumps into the on state during the forward sweep of $V_{\rm g}$ above $V_{\rm c}$ due to the formation of the DW between D and S and falls into the off state during the backward sweep of $V_{\rm g}$ below $-V_{\rm c}$ due to the erasure of the DW. This observation is in agreement with the DW formation and elimination behaviors inferred from the PFM images in Figs. 2(c) and 2(d). Figure 3(d) shows the $I_{\rm s}$–$V_{\rm g}$ curves under different applied $V_{\rm d}$ when $V_{\rm s} = 0$ V with extracted $I_{\rm ds}$–$V_{\rm g}$ curves shown in Fig. 3(e). These curves exhibit the same behaviors as those in Figs. 3(b) and 3(c), indicating the symmetry in electrical characteristics between D and S. Figure 3(f) presents the extracted $I_{\rm ds}$–$V_{\rm s}$ curves under different applied $V_{\rm g}$ when $V_{\rm d} = 0$ V. The field-effect $I_{\rm ds}$ increases with the increase of either $|V_{\rm s}|$ or $V_{\rm g}$. This is because DWs can be regarded as conductive 2D sheets.[13] Thus, their resistances vary with their lateral width which can be tuned by applying biases of different magnitudes between the coplanar electrodes.[17] Higher $V_{\rm g}$ can extend the area of switched domain towards D and S leading to a broader and thus more conductive domain wall.

Fig. 4. Endurance and retention characteristics of the FEDW transistor. (a) Switching number dependence of on- and off-state $I_{\rm ds}$ when $V_{\rm d} = 0$ V and $V_{\rm s} = -6$ V. The inset shows the configured $V_{\rm g}$ waveform during each switching cycle. The on- and off-state $I_{\rm ds}$ characteristics were acquired when $V_{\rm g} = 0$ V after applications of the $+$15 V and $-15$ V pulses, respectively. (b) $I_{\rm ds}$ transient versus time after removal of $+$15 V pulse on G. The inset shows the pulse sequences of $V_{\rm g}$ and $V_{\rm s}$ ($V_{\rm d} = 0$ V).

The endurance characteristic of the FEDW transistor is shown in Fig. 4(a). During the measurement, periodic square waves sketched in the inset were applied to the G electrode while $V_{\rm d}$ and $V_{\rm s}$ kept constant, and $I_{\rm d}$ was intermittently measured against switching cycles when $V_{\rm g} = 0$ V (i.e., $I_{\rm d}=I_{\rm ds}$). The on and off currents are stable within $10^{4}$ switching cycles with an on/off ratio of $\sim$ $100$. To investigate the polarization retention, $I_{\rm d}$ was measured against time after the application of $V_{\rm g}$ (i.e., $I_{\rm d}=I_{\rm ds}$) which turned on the transistor while $V_{\rm d}$ and $V_{\rm s}$ were constant at all time, as shown in Fig. 4(b). $I_{\rm ds}$ drops to the level of the off state after $\sim$ $1$ s, revealing the poor retention of the DW between D and S created by the previous $V_{\rm g}$ pulse. This finding is in agreement with the unusual behavior observed in Fig. 2(c) where the switched domains between D and S contract to disconnect the S electrode. This is mainly because the insulative film cannot provide sufficient free carriers to screen the domain boundary charges resulting in giant depolarization field to restore the switched domains.[27] To improve the poor retention, one possible method is to etch the channel region (the area among D, S, and G) into a mesa with electrodes deposited at the edges of the mesa.[30] With this structure the metal electrodes can screen the domain boundary charges effectively. Besides retention, the on-state $I_{\rm ds}$ is small (below 100 pA when $|V_{\rm ds}|=6$ V) because of the relatively large spacing [$\sim$ $700$ nm, as shown in Fig. 1(c)] between D and S compared with previous works.[13,27] According to the equation of the space-charge-limit current, scaling down of the spacing between D and S may be a feasible way to improve the on-state $I_{\rm ds}$.[30] Although the retention time and on-state $I_{\rm ds}$ of our FEDW transistor are unsatisfying yet, it has shown the tremendous potential to serve as a nonvolatile transistor which plays a key role in in-memory computing hardware.[31,32] In summary, we have fabricated the FEDW transistors at the surface of (110)-oriented BFO thin films. Their on/off states can be controlled by the applied voltage to the G electrode. The working principle is the creation and erasure of domain walls between D and S electrodes under the applied electric fields. The on state can be maintained after the removal of applied voltages because of the polarization retention, which provides a potential solution for in-memory computing circuits. However, the retention needs to be further improved to meet the long-term requirements of the devices for future applications. Acknowledgements. This work was supported by the National Key Basic Research Program of China (Grant No. 2019YFA0308500), and the National Natural Science Foundation of China (Grant No. 61904034). References Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuitsConduction at domain walls in oxide multiferroicsDomain Wall Conductivity in La-Doped

{BiFeO}_{3}

Conduction through 71° Domain Walls in

{BiFeO}_{3}

Thin FilmsTunable Metallic Conductance in Ferroelectric NanodomainsAbove-bandgap voltages from ferroelectric photovoltaic devicesEfficient Photovoltaic Current Generation at Ferroelectric Domain WallsEnhancement of Local Photovoltaic Current at Ferroelectric Domain Walls in BiFeO3Magnetotransport at Domain Walls in

{BiFeO}_{3}

Domain wall magnetoresistance in BiFeO₃ thin films measured by scanning probe microscopySpintronic Functionality of BiFeO₃ Domain WallsCollective Magnetism at Multiferroic Vortex Domain WallsNonvolatile ferroelectric domain wall memoryLow-Voltage Domain-Wall LiNbO₃ MemristorsNonvolatile Ferroelectric‐Domain‐Wall Memory Embedded in a Complex Topological Domain StructureNonvolatile ferroelectric field-effect transistorsIn‐Memory Computing of Multilevel Ferroelectric Domain Wall Diodes at LiNbO₃ InterfacesCurrent change due to artificial patterning of the number of ferroelectric domain walls and nonvolatile memory characteristicsConductive Domain-Wall Temperature Sensors of LiNbO₃ Ferroelectric Single-Crystal Thin FilmsFerroelectric domain walls for nanotechnologyNarrow Waveguide Based on Ferroelectric Domain WallErasable Ferroelectric Domain Wall DiodesElectrical half-wave rectification at ferroelectric domain wallsPersistent conductive footprints of 109° domain walls in bismuth ferrite filmsDepletion Layers and Domain Walls in Semiconducting Ferroelectric Thin FilmsPhysics and Applications of Bismuth FerriteHierarchical Domain Structure and Extremely Large Wall Current in Epitaxial BiFeO₃ Thin FilmsStrain Control of Domain-Wall Stability in Epitaxial

{BiFeO}_{3}

(110) FilmsDomain Control in Multiferroic BiFeO3 through Substrate VicinalityTemporary formation of highly conducting domain walls for non-destructive read-out of ferroelectric domain-wall resistance switching memoriesThe future of ferroelectric field-effect transistor technologyMemory devices and applications for in-memory computing

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