⇦Chinese Physics Letters, 2020, Vol. 37, No. 11, Article code 118501 Surface Modification for WSe$_{2}$ Based Complementary Electronics Ming-Liang Zhang (张明亮), Xu-Ming Zou (邹旭明), and Xing-Qiang Liu (刘兴强)* Affiliations Key Laboratory for Micro/Nano Optoelectronic Devices of Ministry of Education & Hunan Provincial Key Laboratory of Low-Dimensional Structural Physics and Devices, School of Physics and Electronics, Hunan University, Changsha 410082, China Received 11 August 2020; accepted 11 September 2020; published online 8 November 2020 Supported by the National Key Research and Development Program of China (Grant Nos. 2018YFA0703704 and 2018YFB0406603), the National Natural Science Foundation of China (Grant Nos. 61851403, 51872084, 61704052, 61811540408, 51872084, and 61704051), the Key Research and Development Plan of Hunan Province (Grant No. 2018GK2064), and the Natural Science Foundation of Hunan Province (Grant Nos. 2017RS3021 and 2017JJ3033).
*Corresponding author. Email: liuxq@hnu.edu.cn Citation Text: Zhang M L, Zou X M and Liu X Q 2020 Chin. Phys. Lett. 37 118501    Abstract High-performance WSe$_{2}$ complementary transistors are demonstrated on an individual flake by ozone exposure, which relies on the charge transfer mechanism. This technology is readily feasible for modulating the conductivity type in WSe$_{2}$, and the p–n junction presents a high on-off ratio of 10$^{4}$. Based on robust p-type transistors and matched output current of n-type WSe$_{2}$ transistors, the complementary inverter achieves a high voltage gain of 19.9. Therefore, this strategy may provide an avenue for development of high-performance complementary electronics. DOI:10.1088/0256-307X/37/11/118501 PACS:85.35.-p, 85.30.De, 73.22.-f, 73.63.Bd © 2020 Chinese Physics Society Article Text Transition metal dichalcogenide (TMDs) materials have the potential to be used in future low-power complementary nanoelectronics.[1–6] Complementary devices enable low power consumption for integrated circuits, and both p-type and n-type transistors are indispensable cornerstones. WSe$_{2}$ typically presents bipolar transfer characteristics, thus logic electronics with bipolar WSe$_{2}$ transistors have been demonstrated.[7] However, there is a significant band edge shift upon thickness variation of WSe$_{2}$, the conductivity type strongly depends on the thickness.[7,8] Thus, inconclusive electrical performance induced by the thickness variation should be addressed.[9,10] However, due to the poor solid solubility and strong in-panel bonds, it is difficult to modulate the conductivity type of the intrinsic WSe$_{2}$ by the traditional processes. Herein, ultra-thin self-limiting stoichiometric WO$_{x}$ is grown onto WSe$_{2}$ flake by ozone exposure. This strategy can readily eliminate the layer-dependent electrical performance in WSe$_{2}$ transistors, which can be attributed to electron transfer mechanism. The extracted mobility of hole dominant ($\mu_{\rm p}$) region is improved to 41.4 cm$^{2}$$\cdot$V$^{-1}$s$^{-1}$ with an on/off ratio of $\sim$$10^{6}$. In combination with the pattern technique, complementary electronics are fabricated on an individual WSe$_{2}$ flake. The p–n homojunction-based diode achieves a high on/off ratio of 10$^{4}$, and the logic inverters continuously obtain a high gain of 19.9. This work presents an alternative avenue for fabrication of two-dimensional materials based complementary electronics. Figure 1(a) is a schematic of the WSe$_{2}$ transistors, where ozone was used for surface modification of WSe$_{2}$ flakes. Flakes with different thickness are transferred onto a 300-nm SiO$_{2}$/p$^{+}$-Si substrate with mechanically exfoliation method.[11–13] Exposure of WSe$_{2}$ flakes in ozone leads to self-limiting oxidation of WSe$_{2}$ surface layers to tungsten oxides (WO$_{x}$).[10] Figure 1(b) shows the AFM image of the intrinsic few-layered WSe$_{2}$. Figure 1(c) gives the corresponding height information, which indicates a thickness of 5.25 nm with reasonable flat surface. Figure 1(d) is the AFM image after 10 min ozone exposure, indicating a height of 5.89 nm [Fig. 1(e)]. The increment of the height should be induced by the low density of the oxide layer. Figure 1(f) is typical Raman spectra of WSe$_{2}$ flakes measured with the 532 nm excitation wavelengths in the spectral range 100–400 cm$^{-1}$, and the $A_{\rm 1g}$ and $E_{\rm 2g}^{1}$ modes have practically the same frequency. The negligible shift indicates desirable interface quality. Electron-beam lithography (EBL) is introduced to define the contact region of the back-gated transistors. Then Cr (10 nm)/Au (50 nm) electrodes are formed by thermal evaporation, followed by lift-off process, as shown in Fig. 2(a). Figure 2(b) is the transfer characteristics of WSe$_{2}$ transistors with different channel thicknesses. It is confirmed that the transportation type of WSe$_{2}$ transistors is significantly dependent on its thickness.[14,15] With the increment of WSe$_{2}$ thickness, the transportation type of the transistors evolves from p-type to ambipolar and then n-type, indicating strong thickness-dependent carrier transport characteristics in the WSe$_{2}$ transistors. Figure 2(c) shows the plots of electron ($I_{\rm n}$) and hole dominant channel current ($I_{\rm p}$) versus channel thickness, in which $I_{\rm n}$ increases with channel thickness, while the $I_{\rm p}$ obtains a peak value with a channel thickness around 10 nm. Figure 2(d) summarizes the thickness-dependent field-effect mobility of the WSe$_{2}$ transistors.[5,16,17] The extracted mobility of hole dominant ($\mu_{\rm p}$) region decreases from 2.4 to $\sim $0.01 cm$^{2}$$\cdot$V$^{-1}$s$^{-1}$ as the thickness of WSe$_{2}$ increases. Meanwhile, the extracted mobility of electron dominant region ($\mu_{\rm n}$) increases from 0 to 47.8 cm$^{2}$$\cdot$V$^{-1}$s$^{-1}$. The statistical data is obtained from dozens of devices. The transportation type of WSe$_{2}$ transistors versus channel thickness can be attributed to the significant band edge shift in the thickness variation of two-dimensional materials.[14,18]
cpl-37-11-118501-fig1.png
Fig. 1. Schematic diagram and characterization of the WSe$_{2}$ flakes. (a) Schematic image of WSe$_{2}$ transistors. (b) and (c) AFM image and the height information of the intrinsic WSe$_{2}$ flakes. (d) and (e) AFM image and the height information of the WSe$_{2}$ flakes after ozone treatment. (f) Raman spectra of WSe$_{2}$ flakes before and after ozone exposure.
cpl-37-11-118501-fig2.png
Fig. 2. Thickness-dependent transport characteristics of the WSe$_{2}$ transistors. (a) Optical image of the WSe$_{2}$ transistor, with the scale bar 5 µm. (b) Transfer characteristics of WSe$_{2}$ transistors with different channel thicknesses. (c) The plots of electron ($I_{\rm n}$) and hole dominant channel current ($I_{\rm p}$) versus channel thickness at $V_{\rm D}= 1$ V. (d) The extracted mobility of electron ($\mu_{\rm n}$) and hole dominant ($\mu_{\rm p}$) region versus channel thickness at $V_{\rm D}= 1$ V.
Tungsten oxides (WO$_{x})$ can be used as controlled charge transfer dopants for p-type WSe$_{2}$ transistors.[19,20] Exposure of atomically thin WSe$_{2}$ transistors to ozone at 80 ℃ leads to self-limiting stoichiometric WO$_{x}$ films on the WSe$_{2}$ surfaces. WO$_{x}$-coated WSe$_{2}$ is highly hole-doped due to the surface electron transfer from the underlying WSe$_{2}$ to the high electron affinity WO$_{x}$, and thus the $I_{\rm p}$ is enhanced with degraded $I_{\rm n}$.[21–23] Figure 3(a) shows the evolution of transfer characteristics for WSe$_{2}$ transistors after intermittent ozone exposure at 80 ℃. With the increasing oxidation time, the properties of WSe$_{2}$ transformed from ambipolar to p-type at first. After an ozone treatment time of 10 min, the WO$_{x}$-coated WSe$_{2}$ transistor has obvious p-type characteristics with a hole mobility of 41.4 cm$^{2}$$\cdot$V$^{-1}$s$^{-1}$ and an on/off ratio of $\sim$$10^{6}$, which are one order of magnitude larger than those of the pristine multilayer WSe$_{2}$ transistors. With the further increase of oxidation time, the $I_{\rm n}$ starts to increase and the on/off ratio of the WSe$_{2}$ transistor decreases gradually. Finally, negligible on-off characteristics can be further observed as the oxidation time exceeds 30 min. As shown in Fig. 3(b), the linear and symmetric $I_{\rm D}$–$V_{\rm D}$ characteristics suggest the significant reduction of the contact resistance in the WSe$_{2}$ transistors with the WO$_{x}$ layer.[24,25] At first, the $I_{\rm p}$ increases exponentially with the increasing oxidation time. The current then subsequently gradually leveled off, as shown in Fig. 3(c). At the n side, the current is obviously decreasing with the increase of oxidation time. When the oxidation time exceeds 10 min, the $I_{\rm n}$ starts to increase again until negligible on/off ratio can be observed. Figure 3(d) shows the experimentally extracted field-effect mobility of WSe$_{2}$ transistors by intermittent ozone exposure from 0 to 20 min. The curve indicates that the n-type dominant characteristics of the WSe$_{2}$ transistors become of p-type. Complementary logic electronics are constructed based on the quasi-n-type and quasi-p-type regions of an individual WSe$_{2}$ flake. The WSe$_{2}$ channel is patterned by e-beam lithography, and then 20 nm Al$_{2}$O$_{3}$ was deposited on half of the channel by atomic layer deposition. Thus, the Al$_{2}$O$_{3}$ covered region cannot be affected by the ozone exposure. The device was then exposed to ozone at 80 ℃ for 10 min, leading to abrupt p–n homojunction on atomic level, as shown in Fig. 4(a). Figure 4(b) exhibits gate tunable rectification characteristics of the WSe$_{2}$ p–n homojunction with gate voltages ranging from $-$60 to 0 V. The p–n homojunction obtains the remarkable rectification ratio of $> 10^{4}$ (defined by the ratio of the forward current to the reverse current at the same bias voltage) as $V_{\rm G}=-60$ V. Figure 4(c) plots the rectification of the WSe$_{2}$-based p–n homojunction as a function of gate voltage. As the gate changes from 0 to $-$60 V, the carrier density in the channel increases sharply, leading to the increase of rectification ratio. The inset in Fig. 4(c) is the optical image of the WSe$_{2}$-based complementary inverter. An inverter gate is demonstrated using one quasi-n-type and one quasi-p-type transistor connected in series. The n-type one is grounded and the supplied voltage ($V_{\rm DD}$) is applied to the p-type one. Both quasi-n-type and quasi-p-type transistors are controlled by the global back gate that serves as the input voltage ($V_{\rm IN}$) terminal, as shown in Fig. 4(d). The transfer characteristics ($V_{\rm OUT}$ versus $V_{\rm IN}$) of the complementary inverter as a function of $V_{\rm DD}$ are shown in Fig. 4(e). The circuit diagram of the complementary inverter is shown in the inset of Fig. 4(e). The inverter exhibits sharp transition between high and low level. The noise margin is the maximum voltage amplitude of extraneous signal that can be algebraically added to the noise-free worst-case input level without causing the output voltage to deviate from the allowable logic voltage level. The high-noise margins (NM$_{\rm H}$) and low-noise margins (NM$_{\rm L}$) are extracted from the voltage transfer characteristic and its mirror reflection curve, and NM$_{\rm L}= 0.39V_{\rm DD}$ and NM$_{\rm H}= 0.41V_{\rm DD}$ are obtained at $V_{\rm DD}= 12$ V, indicating the robustness of the inverter towards noise. The inverter simultaneously demonstrates a total margin nearly 79.8% and an almost ideal noise margin of 0.4 $V_{\rm DD}$ at $V_{\rm DD}=12$ V. Figure 4(f) is the voltage gain of the inverter, which is calculated by taking the derivation of the voltage transfer curves, indicating that the voltage gain increases with the increasing $V_{\rm DD}$, and a voltage gain 19.9 is achieved at $V_{\rm DD} =12$ V. Table 1 gives the performance comparisons among the 2D material transistors to state the significance of this work. These results indicate that WSe$_{2}$-based complementary electronics are promising for future applications.
cpl-37-11-118501-fig3.png
Fig. 3. The evolution trend of $I_{\rm D}$–$V_{\rm G}$ characteristics of WSe$_{2}$ transistors as exposed in ozone at 80 ℃. (a) $I_{\rm D}$–$V_{\rm G}$ curves of WSe$_{2}$ transistors upon intermittent ozone exposure from 0 to 30 min. (b) $I_{\rm D}$–$V_{\rm G}$ curves of WSe$_{2}$ transistors with V$_{\rm G}$ ranging from 0 to $-$80 V with an exposure time of 10 min. (c) $I_{\rm n}$ and $I_{\rm p}$ of the ambipolar WSe$_{2}$ transistors by intermittent ozone exposure from 0 to 20 min at $V_{\rm D}= 1$ V. (d) Plots of the extracted field-effect mobility of WSe$_{2}$ transistors versus ozone exposure time at $V_{\rm D}= 1$ V.
cpl-37-11-118501-fig4.png
Fig. 4. WSe$_{2}$-based logic p–n homojunction devices. (a) Schematic image of WSe$_{2}$ transistors with 20 nm Al$_{2}$O$_{3}$ layer as mask. (b) The influence of gate potential on the $I$–$V$ characteristics of the p–n homojunction. (c) The plots of gate tunable rectification ratio $I_{\rm on}/I_{\rm off}$ of the WSe$_{2}$ p–n homojunction. The inset is the optical image of the WSe$_{2}$-based complementary inverter. The scale bar is 20 µm. (d) Schematic of the device structure for complementary WSe$_{2}$-based inverter. (e) The voltage output characteristics of the WSe$_{2}$-based complementary inverter at different supply $V_{\rm DD}$. (f) Extracted voltage gain of the inverter.
Table 1. Comparison of the device performance with other works.
Material Dopant Device type On/off ratio Voltage gain
This work WSe$_{2}$ O$_{3}$ homojunction 10$^{4}$ 19.9
Xue et al.[26] MoSe$_{2}$/ WSe$_{2}$ NA heterojunction 10$^{4}$ NA
Han et al.[27] BP K homojunction 10$^{4}$ 5
Yu et al.[28] WSe$_{2}$ F$_{4}$TCNQ homojunction 10$^{8}$ 38
Sun et al.[29] WSe$_{2}$ CTAB homojunction 10$^{5}$ NA
Tosun et al.[30] WSe$_{2}$ K homojunction 10$^{4}$ 12
Guo et al.[31] WSe$_{2}$/ZnO NA heterojunction 10$^{4}$ NA
In summary, we have adopted a self-limiting surface oxidation of WO$_{x}$ as the charge transfer layer in WSe$_{2}$-based complementary electronics. Due to the large electron affinity of WO$_{x}$, WSe$_{2}$ is heavily p-doped by surface charge transfer.[14] Complementary devices were subsequently fabricated on an individual WSe$_{2}$ flake, realizing a p–n homojunction with a high rectification and a logic inverter with high voltage gain. This study promises a feasible approach to modulate the electrical performance of two-dimensional materials-based transistors for complementary logic devices. References Single-layer MoS2 transistorsLarge-Area 2-D Electronics: Materials, Technology, and DevicesElectronics based on two-dimensional materialsIntegrated Circuits Based on Bilayer MoS 2 TransistorsHigh-Performance Single Layered WSe 2 p-FETs with Chemically Doped ContactsHigh Performance Multilayer MoS 2 Transistors with Scandium ContactsCarrier Type Control of WSe 2 Field-Effect Transistors by Thickness Modulation and MoO 3 Layer DopingAnomalous Raman spectra and thickness-dependent electronic properties of WSe 2 Self-Limiting Layer-by-Layer Oxidation of Atomically Thin WSe 2Self-Limiting Oxides on WSe 2 as Controlled Surface Acceptors and Low-Resistance Hole ContactsPreparation and Applications of Mechanically Exfoliated Single-Layer and Multilayer MoS 2 and WSe 2 NanosheetsUltrasensitive photodetectors based on monolayer MoS2Single-Layer MoS 2 PhototransistorsEvolution of Electronic Structure in Atomically Thin Sheets of WS 2 and WSe 2Excited Excitonic States in 1L, 2L, 3L, and Bulk WSe 2 Observed by Resonant Raman SpectroscopyControllable Nondegenerate p-Type Doping of Tungsten Diselenide by OctadecyltrichlorosilaneHigh-Mobility Holes in Dual-Gated WSe 2 Field-Effect TransistorsElectronic structure of transition metal dichalcogenides monolayers 1H-MX2 (M = Mo, W; X = S, Se, Te) from ab-initio theory: new direct band gap semiconductorsVLSI-Compatible Carbon Nanotube Doping Technique with Low Work-Function Metal OxidesAir stable n-doping of WSe2 by silicon nitride thin films with tunable fixed charge densityThermal Oxidation of WSe 2 Nanosheets Adhered on SiO 2 /Si SubstratesLaser-assisted oxidation of multi-layer tungsten diselenide nanosheetsEffect of oxygen and ozone on p-type doping of ultra-thin WSe 2 and MoSe 2 field effect transistorsSwitching Mechanism in Single-Layer Molybdenum Disulfide Transistors: An Insight into Current Flow across Schottky BarriersThickness Scaling Effect on Interfacial Barrier and Electrical Contact to Two-Dimensional MoS 2 LayersA MoSe 2 /WSe 2 Heterojunction-Based Photodetector at Telecommunication WavelengthsSurface Functionalization of Black Phosphorus via Potassium toward High-Performance Complementary DevicesHigh-Performance WSe 2 Complementary Metal Oxide Semiconductor Technology and Integrated CircuitsLateral 2D WSe 2 p–n Homojunction Formed by Efficient Charge‐Carrier‐Type Modulation for High‐Performance OptoelectronicsHigh-Gain Inverters Based on WSe 2 Complementary Field-Effect TransistorsLight‐Driven WSe 2 ‐ZnO Junction Field‐Effect Transistors for High‐Performance Photodetection
[1] Radisavljevic B et al. 2011 Nat. Nanotechnol. 6 147
[2] Hsu S A et al. 2013 Proc. IEEE 101 1638
[3] Fiori G et al. 2014 Nat. Nanotechnol. 9 768
[4] Wang H et al. 2012 Nano Lett. 12 4674
[5] Fang H et al. 2012 Nano Lett. 12 3788
[6] Das S et al. 2013 Nano Lett. 13 100
[7] Zhou C et al. 2016 Adv. Funct. Mater. 26 4223
[8] Sahin H et al. 2013 Phys. Rev. B 87 165409
[9] Yamamoto M et al. 2015 Nano Lett. 15 2067
[10] Yamamoto M et al. 2016 Nano Lett. 16 2720
[11] Li H et al. 2014 Acc. Chem. Res. 47 1067
[12] Lopez-Sanchez O et al. 2013 Nat. Nanotechnol. 8 497
[13] Yin Z et al. 2012 ACS Nano 6 74
[14] Zhao W et al. 2013 ACS Nano 7 791
[15] del Corro E et al. 2014 ACS Nano 8 9629
[16] Kang D H et al. 2015 ACS Nano 9 1099
[17] Movva H C et al. 2015 ACS Nano 9 10402
[18] Kumar A and Ahluwalia P K 2012 Eur. Phys. J. B 85 186
[19] Suriyasena Liyanage L et al. 2014 Nano Lett. 14 1884
[20] Chen K et al. 2014 APL Mater. 2 092504
[21] Liu Y et al. 2015 Nano Lett. 15 4979
[22] Tan C et al. 2016 Appl. Phys. Lett. 108 083112
[23] Wang S F et al. 2016 Phys. Chem. Chem. Phys. 18 4304
[24] Liu H et al. 2014 ACS Nano 8 1031
[25] Li S L et al. 2014 ACS Nano 8 12836
[26] Xue H et al. 2018 Adv. Funct. Mater. 28 1804388
[27] Han C et al. 2017 Nano Lett. 17 4122
[28] Yu L L et al. 2015 Nano Lett. 15 4928
[29] Sun J C et al. 2020 Adv. Mater. 32 1906499
[30] Tosun M et al. 2014 ACS Nano 8 4948
[31] Guo N et al. 2020 Adv. Sci. 7 1901637