Improvement of Performance of HfS$_{2}$ Transistors Using a Self-Assembled Monolayer as Gate Dielectric

Wen-Lun Zhang(张文伦)$^{\hyperlink{s}{**}}$

doi:10.1088/0256-307X/36/6/067301

⇦Chinese Physics Letters, 2019, Vol. 36, No. 6, Article code 067301⇨ Improvement of Performance of HfS$_{2}$ Transistors Using a Self-Assembled Monolayer as Gate Dielectric * Wen-Lun Zhang (张文伦)** Affiliations Department of Electrical and Electronic Engineering, Tokyo Institute of Technology, Meguro, Tokyo 152-8552, Japan Received 21 March 2019, online 18 May 2019 ^*Supported by the Japan Society for the Promotion of Science under Grant No JP25107004.
^**Corresponding author. Email: zhang.w.ai@m.titech.ac.jp Citation Text: Zhang W L 2019 Chin. Phys. Lett. 36 067301 Abstract This work details a study based on HfS$_{2}$ transistors utilizing an n-octadecylphosphonic acid-based self-assembled monolayer (SAM) as the gate dielectric. The fabrication of the SAM-based two-dimensional (2D) material transistor is simple and can be used to improve the quality of the interface of air-sensitive 2D materials. In comparison to HfS$_{2}$ transistors utilizing a conventional Al$_{2}$O$_{3}$ gate insulator by atomic layer deposition, HfS$_{2}$ transistors utilizing an SAM as the gate dielectric can reduce the operation region from 4 V to 2 V, enhance the field-effect mobility from 0.03 cm$^{2}$/Vs to 0.75 cm$^{2}$/Vs, improve the sub-threshold swing from 404 mV/dec to 156 mV/dec, and optimize the hysteresis to 0.03 V, thus demonstrating improved quality of the semiconductor/insulator interface. DOI:10.1088/0256-307X/36/6/067301 PACS:73.63.Bd, 73.40.Qv, 68.35.Ct © 2019 Chinese Physics Society Article Text Since the first isolation of graphene from graphite,[1] tremendous interest has been taken in the research of two-dimensional (2D) materials due to their atomic layer thickness, which perfectly matches the policy of device scaling in the electronic industry.[2] Another branch of 2D materials, namely transition metal dichalcogenides (TMDs), show promise as an alternative to silicon-based 2D materials because of their high electron mobility and reasonable band gap. In recent years, transistors fabricated by 2D materials such as MoS$_{2}$,[3] WSe$_{2}$,[4] and black phosphorus (BP)[5] have exhibited a very high performance, showing promise for future low-power digital applications. In this study, the TMD material used for device fabrication is HfS$_{2}$, a semiconducting TMD expected to have high acoustic phonon-limited electron mobility over 1800 cm$^{2}$/Vs.[6] However, extensive research indicated that 2D materials are usually not compatible with traditional high-$\kappa$ dielectrics. High-$\kappa$ dielectrics deposited on 2D materials by atomic layer deposition (ALD) tend to suffer from the presence of pinhole defects caused by the lack of nucleation sites due to the dangling bond free surface, resulting in the inferior performance of top-gated 2D material transistors.[7] Even in 2D material transistors using a high-$\kappa$ gate dielectric within a back-gate structure, defect charges and trap states at the 2D material channel/insulator interface exist. These defect charges and interface trap states not only deteriorate the operation in the sub-threshold region but also act as scattering centers, leading to a sub-threshold swing (SS) over the ideal 60 mV/dec and a degraded electron mobility in the device. One possible solution is to insert a buffer layer, such as Y$_{2}$O$_{3}$, between the gate insulator and the 2D material channel, which significantly improves the performance in top-gated transistors and lowers the interface states.[8] In another study, h-BN was transferred onto a 2D material channel as an encapsulation layer or as a back-gate dielectric to construct a van der Waals heterostructure. The 2D material transistors composed of h-BN show higher electron mobility, optimized SS, and reduced hysteresis.[9] However, the dry transfer process is time-consuming, and it is difficult to control the flake thickness on polydimethylsiloxane (PDMS).[10] Additionally, some ambient-environment-sensitive materials, such as HfS$_{2}$ and BP, are oxidized during the transfer process, resulting in degraded electrical properties.[11] Therefore, a high-quality 2D material channel/insulator interface without complicated transfer process is required for transistors using these sensitive materials. Klauk et al.[12] proposed complementary high-performance circuits using organic-based self-assembled monolayers (SAMs), for example, n-octadecylphosphonic acid (ODPA) SAM, and showed that the gate leakage is much lower than with a silane-based SAM or a plasma-grown AlO$_{x}$ oxide layer. Kawanago et al.[13] introduced an SAM-based dielectric into MoS$_{2}$ transistors, and the small SS operation without hysteresis ensured a good MoS$_{2}$/SAM interface property. 2D transistors using SAMs as the gate dielectric do not require a sophisticated transfer process, offering a possible solution to the interface problems of HfS$_{2} $ transistors. In this work, the fabrication of HfS$_{2}$ transistors was carried out using an SAM as the gate dielectric. The process flow of the fabrication process is shown in Fig. 1. Firstly, the gate electrode was designed by electron beam lithography (EBL), and a 40-nm layer of Al was deposited on a SiO$_{2}$ (90 nm)/Si substrate by electron beam evaporation. Similarly, Cr/Au (20 nm/50 nm) was deposited on the contact part of Al prepared for electrical measurement. After the lift-off process, the substrate was exposed to O$_{2}$ plasma (plasma power: 200 W, $O_{2}$ flow: 100 sccm, duration: 20 min) to grow AlO$_{x}$ on the Al surface. Then the substrate was immersed in 5 mM solution of ODPA in 2-propanol for 16 h. The phosphonic acid-based SAM grows exclusively on the metal oxides, leaving SiO$_{2}$ and Au surfaces uncovered for electrical measurement. After the growth of the SAM, the substrate was rinsed by 2-propanol and baked on a hot plate at 100$^{\circ}\!$C for 10 min. HfS$_{2}$ flakes were randomly transferred onto the substrate by PDMS after mechanical exfoliation using scotch tape, and appropriate flakes located just above the Al/AlO$_{x}$/SAM stacked gate electrode were used to fabricate transistors. The whole transfer process was carried out very quickly to avoid degradation of HfS$_{2}$ flakes by exposure to air. After that, the S/D electrodes were designed by EBL and deposited with a 100-nm layer of Au because Au electrodes have a lower gate leakage than Ti electrodes. In the next step, a 10-nm layer of HfO$_{2}$ was deposited on the substrate by ALD at 150$^{\circ}\!$C as a passivation layer to protect the HfS$_{2}$ flakes from atmospheric contaminants. After etching the contact hole of S/D/G for measurements, the devices were finally annealed in a vacuum at 250$^{\circ}\!$C to enhance the performance.

Fig. 1. Fabrication process of HfS$_{2}$ transistor using SAM as gate dielectric.

Figure 2(a) shows the atomic force microscope (AFM) image of the fabricated device. The thickness of the HfS$_{2}$ flake shown along the red dotted line was measured to be around 11.5 nm, and the channel length of the HfS$_{2}$ transistor was designed to be 1 µm. The cross-section shown along the blue dotted line in Fig. 2(a) was characterized using a transmission electron microscope (TEM), and the image is shown in Fig. 2(b). From the TEM image, the thicknesses of AlO$_{x}$ and SAM are found to be around 6 nm, and the thickness of HfS$_{2}$ is found to be 12 nm, which are consistent with the AFM result. The surface of the SAM is flat, thus avoiding surface roughness scattering and enhancing the device electron mobility. The interface quality of HfS$_{2}$/SAM is good because the surfaces of both the organic SAM and 2D HfS$_{2}$ do not contain dangling bonds, which make fewer trap states and scattering centers, leading to an increased electron mobility. Since the thickness of the native oxide AlO$_{x}$ through O$_{2}$ plasma treatment[12] is 3.6 nm, the thickness of the SAM layer is estimated to be around 2.4 nm. Thus the total capacitance of the gate electrode is calculated to be 0.65 µF/cm$^{2}$ by the series capacitance of AlO$_{x}$ and SAM layers, where the relative permittivities[14] of AlO$_{x}$ and ODPA-based SAM are 9 and 2.5, respectively.

Fig. 2. (a) The AFM image of fabricated HfS$_{2}$ transistor. The flake thickness was measured along the red dotted line. (b) The TEM image of the cross-section along the blue dotted line in (a).

Fig. 3. Electrical characteristics of the back-gated HfS$_{2}$ transistor utilizing 10 nm ALD-deposited Al$_{2}$O$_{3}$ as gate dielectric: (a) transfer curves, (b) output curves, (c) calculated SS from (a).

Figure 3 demonstrates the electrical characteristics of a back-gated HfS$_{2}$ transistor utilizing a 10-nm layer of conventional ALD-deposited Al$_{2}$O$_{3}$ as the gate dielectric. The Al$_{2}$O$_{3}$ was deposited by 100 cycles of precursors using trimethylaluminum and H$_{2}$O at 250$^{\circ}\!$C. The contact electrodes of this transistor were Ti/Pd/Au (20 nm/20 nm/60 nm), and the gate capacitance was calculated to be 0.8 µF/cm$^{2}$ by the plane-parallel capacitor model. As shown in Fig. 3(a), the on/off ratio is over 10$^{4}$, and a current of 6.5 nA/$\,µ$m can be observed at $V_{\rm gs}=4$ V and $V_{\rm ds}=1$ V. A hysteresis of about 0.14 V at the threshold voltage can be detected as shown in Fig. 3(c), and the SS minimum is 404 mV/dec for this system. The relatively large hysteresis and SS indicate that plenty of trap states exist at the interface between the ALD-deposited high-$\kappa$ dielectric and the HfS$_{2}$ channel. Figure 4 demonstrates the electrical characteristics of the HfS$_{2}$ transistor utilizing an SAM as the gate dielectric in Fig. 2. Compared to the one utilizing a conventional ALD-deposited Al$_{2}$O$_{3}$ gate dielectric, some improvements in electrical performance can be verified in the HfS$_{2}$ transistor utilizing an SAM as the dielectric. The operating region is reduced to 0–2 V even though the gate capacitance is smaller, and the on/off ratio of the transistor exceeds 10$^{6}$, along with a current over 170 nA/$\,µ$m. The decreased off-state current of the HfS$_{2}$ transistor indicates that less electron hopping occurs via the trap states. The hysteresis at the threshold voltage decreases to 0.03 V, which significantly improves the stability of the transistor as an electrical switch. Moreover, this transistor exhibits an SS minimum of 156 mV/dec and a relatively long steep slope region with an SS of $\sim$170 mV/dec within three decades of channel current. The field-effect mobility of the HfS$_{2}$ transistors is calculated by $$\begin{align} \mu_{\rm FE} =\Big[\frac{dI_{\rm ds}}{dV_{\rm gs}}\Big]\times\Big[{\frac{L}{WC_{\rm ox} V_{\rm ds}}}\Big],~~ \tag {1} \end{align} $$ where $C_{\rm ox}$ denotes the capacitance of the gate stack, and $L$ and $W$ represent the channel length and width, respectively. The peak mobility of the HfS$_{2}$ transistor utilizing the ALD-deposited gate dielectric is 0.03 cm$^{2}$/Vs, while altering the gate dielectric to an SAM layer enhances the mobility of the transistor to 0.75 cm$^{2}$/Vs, mainly because of the reduced scattering centers as compared to the ALD-deposited gate dielectric.[15] Furthermore, the Au electrodes contribute a lower contact resistance than the Ti electrodes, which may be another reason for the increased device mobility.[16] The interface trap density is evaluated from the SS of transistors using Eq. (2), and disregarding the semiconductor depletion capacitance from the relatively thick HfS$_{2}$ channel, $$\begin{align} {\rm SS}=\frac{kT}{q}\ln 10\cdot\Big(1+\frac{qN_{\rm it}}{C_{\rm ox}}\Big),~~ \tag {2} \end{align} $$ where $q$ represents the elementary charge, $k$ is the Boltzmann constant, $T$ is the temperature in Kelvin degree, and $N_{\rm it}$ represents the interface trap density.[15] The value of $N_{\rm it}$ is reduced from $2.86 \times 10^{13}$ eV$^{-1}\cdot$cm$^{-2}$ to $1.05 \times 10^{13}$ eV$^{-1}\cdot$cm$^{-2}$, indicating that a superior interface quality could be achieved by utilizing an SAM to fabricate 2D material transistors rather than conventional ALD-deposited high-$\kappa$ gate insulators.

Fig. 4. Electrical characteristics of the HfS$_{2}$ transistor utilizing SAM as gate dielectric: (a) transfer curves, (b) output curves, (c) calculated SS from (a).

In traditional semiconductor physics, the interface trap states always originate from the dangling bonds at the semiconductor/insulator interface, and the operation of the HfS$_{2}$ transistor can also be explained using these theories. If a positive bias is applied to the back-gate electrode of the HfS$_{2}$ transistor, effective amounts of carriers will accumulate in the vicinity of the interface of the HfS$_{2}$ channel. Then the generation of carriers relies on the external injection of charges from the contact by a drain bias, which implements the electrical switching of the HfS$_{2}$ transistor. In the case of an HfS$_{2}$ transistor using ALD-deposited Al$_{2}$O$_{3}$ as the gate dielectric, only the Al$_{2}$O$_{3}$ back-gate dielectric contributes the total gate capacitance without considering the depletion capacitance of the HfS$_{2}$ channel under an ideal condition. However, structural defects in high-$\kappa$ Al$_{2}$O$_{3}$ dielectric, oxidation-induced defects in HfS$_{2}$ during the fabrication process, or other similar defects of bond breaking can be charged or discharged, depending on the surface potential. Therefore, the electrical communication of these trap states at the interface produces an extra series capacitance of $qN_{\rm it}$, and the second term in the bracket of Eq. (2) deteriorates the SS from the ideal condition. Furthermore, the trap states are occupied by the electrons flowing in the HfS$_{2}$ channel at the forward sweep of the transistor operation, so that these states are neutralized and not emitted quickly in the backward sweep transistor operation. The potential difference in the HfS$_{2}$ channel between the forward and backward sweeps varies the threshold voltage of the transistor, which results in the hysteresis in the HfS$_{2}$ transistor. In comparison, an SAM is an organized layer of amphiphilic molecules with intact structure, which means that no defects such as dangling bonds exist. With the introduction of the AlO$_{x}$/SAM gate dielectric stack, minimization of interface traps can be achieved, reducing the operation SS and hysteresis. In summary, the experimental results of HfS$_{2}$ transistors fabricated with AlO$_{x}$/SAM as the gate dielectric have been reported and discussed. Optimized hysteresis, reduced SS, and increased field-effect mobility are achieved in the SAM-based HfS$_{2}$ transistor, indicating that the interface between the HfS$_{2}$ channel and the SAM-based dielectric is better than that between the HfS$_{2}$ channel and the conventional high-$\kappa$ insulator. Compared to other interface engineering methods such as Y$_{2}$O$_{3}$ insertion and h-BN encapsulation, the fabrication process of the SAM-based 2D material transistor is simpler and quicker, making it an optimal method for improving the interface quality of air-sensitive 2D materials. References Electric Field Effect in Atomically Thin Carbon FilmsSingle-layer MoS2 transistorsHigh-Performance Single Layered WSe ₂ p-FETs with Chemically Doped ContactsBlack phosphorus field-effect transistorsTwo-dimensional semiconductors with possible high room temperature mobilityImproved Growth Behavior of Atomic-Layer-Deposited High- k Dielectrics on Multilayer MoS ₂ by Oxygen Plasma PretreatmentToward High-Performance Top-Gate Ultrathin HfS ₂ Field-Effect Transistors by Interface EngineeringComparison of trapped charges and hysteresis behavior in hBN encapsulated single MoS ₂ flake based field effect transistors on SiO ₂ and hBN substratesDeterministic transfer of two-dimensional materials by all-dry viscoelastic stampingOxidation Effect in Octahedral Hafnium Disulfide Thin FilmUltralow-power organic complementary circuitsUtilizing self-assembled-monolayer-based gate dielectrics to fabricate molybdenum disulfide field-effect transistorsLowering interface state density in carbon nanotube thin film transistors through using stacked Y ₂ O ₃ /HfO ₂ gate dielectricUltrasensitive Phototransistors Based on Few-Layered HfS ₂

[1]	Novoselov K S, Geim A K, Morozov S V, Jiang D, Zhang Y, Dubonos S V, Grigorieva I V and Firsov A A 2004 Science 306 666
[2]	Dennard R H, Gasensslen F H, Yu H, Rideout V L, Bassous E and Leblanc A R 1974 IEEE Trans. Solid-State Circuits SC-9 256
[3]	Radisavljevic B, Radenovic A, Brivio J, Giacometti V and Kis A 2011 Nat. Nanotechnol. 6 147
[4]	Fang H, Chuang S, Chang T C, Takei K, Takahashi T and Javey A 2012 Nano Lett. 12 3788
[5]	Li L, Yu Y, Ye G J, Ge Q, Ou X, Wu H, Feng D, Chen X H and Zhang Y 2014 Nat. Nanotechnol. 9 372
[6]	Zhang W, Huang Z, Zhang W and Li Y 2014 Nano Res. 7 1731
[7]	Yang J, Kim S, Choi W, Park S H, Jung Y, Cho M and Kim H 2013 ACS Appl. Mater. Interfaces 5 4739
[8]	Xu K, Huang Y, Chen B, Xia Y, Lei W, Wang Z, Wang Q, Wang F, Yin L and He J 2016 Small 12 3106
[9]	Lee C, Rathi S, Khan M A, Lim D, Kim Y, Yun S J, Youn D, Watanabe K, Taniguchi T and Kim G 2018 Nanotechnology 29 335202
[10]	Castellanos-Gomez A, Buscema M, Molenaar R, Singh V, Janssen L, van der Zant H S J and Steele G A 2014 2D Mater. 1 011002
[11]	Chae S H, Jin Y, Kim T S, Chung D S, Na H, Nam H, Kim H, Perello D J, Jeong H Y, Ly T H and Lee Y H 2016 ACS Nano 10 1309
[12]	Klauk H, Zschieschang U, Pflaum J and Halik M 2007 Nature 445 745
[13]	Kawanago T and Oda S 2016 Appl. Phys. Lett. 108 041605
[14]	Salinas M 2014 Interface Engineering with Self-Assembled Monolayers for Organic Electronics (Erlangen: FAU University Press)
[15]	Xu L, Gao N, Zhang Z and Peng L 2018 Appl. Phys. Lett. 113 083105
[16]	Xu K, Wang Z, Wang F, Huang Y, Wang F, Yin L, Jiang C and He J 2015 Adv. Mater. 27 7881