⇦Chinese Physics Letters, 2018, Vol. 35, No. 2, Article code 027302 Concise Modeling of Amorphous Dual-Gate In-Ga-Zn-O Thin-Film Transistors for Integrated Circuit Designs * Can Li(李璨), Cong-Wei Liao(廖聪维)**, Tian-Bao Yu(于天宝), Jian-Yuan Ke(柯建源), Sheng-Xiang Huang(黄生祥), Lian-Wen Deng(邓联文) Affiliations School of Physics and Electronics, Central South University, Changsha 410083 Received 29 August 2017 *Supported by the National Key Research and Development Program of China under Grant No 2017YFA0204600, the National Natural Science Foundation of China under Grant No 61404002, and the Science and Technology Project of Hunan Province under Grant No 2015JC3041.
**Corresponding author. Email: hustliao@126.com Citation Text: Li C, Liao C W, Yu T B, Ke J Y and Huang S X et al 2018 Chin. Phys. Lett. 35 027302 Abstract An analytical model for current–voltage behavior of amorphous In-Ga-Zn-O thin-film transistors (a-IGZO TFTs) with dual-gate structures is developed. The unified expressions for synchronous and asynchronous operating modes are derived on the basis of channel charges, which are controlled by gate voltage. It is proven that the threshold voltage of asynchronous dual-gate IGZO TFTs is adjusted in proportion to the ratio of top insulating capacitance to the bottom insulating capacitance $(C_{\rm TI}/C_{\rm BI})$. Incorporating the proposed model with Verilog-A, a touch-sensing circuit using dual-gate structure is investigated by SPICE simulations. Comparison shows that the touch sensitivity is increased by the dual-gate IGZO TFT structure. DOI:10.1088/0256-307X/35/2/027302 PACS:73.40.Qv, 71.23.An, 85.60.Pg © 2018 Chinese Physics Society Article Text Amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) show great potential for mass production of active matrix flat panel display (AMFPD),[1,2] owing to the high mobility, excellent uniformity, and low manufacturing cost.[3] In recent years, IGZO TFTs with dual-gate (DG) structure attract enormous attention, due to the improved electrical performance.[4,5] Baek et al. demonstrated that the threshold voltage of DG IGZO TFTs can be adjusted by changing base voltage.[6] Wang et al. showed a new AMOLED pixel circuit with DG IGZO TFTs.[7] However, few works have been involved for modeling of current–voltage characteristics of DG IGZO TFTs to date. Due to the lack of an analytical model, there are great difficulties to simulate DG IGZO TFT integrated circuits. Recently, widespread attention has been paid to TFT integrated touch sensors for consuming electronics. Nakamura proposed an in-cell touch sensor array using LTPS TFTs, which showed a good measurement result.[8] However, the schematic seems slightly complicated, as many elements are required for sensing pixel circuit, such as a storing capacitance, a pre-charging, a reading-out TFT, and an amplifier circuit. Thus Cheu et al. proposed a simpler sensing pixel circuit where only four TFTs and one coupling capacitance were used.[9] In addition, Brown et al. proposed 1TFT-1capacitance touch sensing circuit with the LTPS TFT technology.[10] However, the research of touch sensor using IGZO TFTs is not enough, and specifically there are fewer studies on touch sensor using DG IGZO TFTs. Furthermore, as the requirements for the switching and driving transistors are different, the dimension and configuration for the DG IGZO TFTs should be carefully chosen. Figure 1 shows the simplified cross sectional view of DG IGZO TFTs, and Table 1 lists the geometrical parameters. The active layer is controlled by two separated gates, i.e., bottom gate (BG) and top gate (TG).[11] In this study, floating gate effects are avoided because both the top and the bottom gate electrodes are connected with specific voltage source. As the two gates can be applied with the same or different controlling voltages, unified current–voltage expressions will be derived on the basis of channel charge–voltage relationship in the following.
Table 1. Geometrical parameters of dual-gate IGZO TFTs.
Parameter Value
Top/bottom gate thickness (nm/nm) 100/100
Gate insulator thickness (nm) 200
IGZO layer thickness (nm) 30
Channel width/length (μm/μm) 60/10
The $y$ direction is along the side of the IGZO film from the source to the drain electrodes. The channel length is $L$, and the thickness is $t_{\rm s}$ as shown in Fig. 1. Here $y=0$ and $y=L$ indicate the regional boundary of channel to source and of channel to drain, $C_{\rm TI}$, $C_{\rm BI}$ and $C_{\rm dep}$ are the capacitance values per unit area for the top insulator, bottom insulator, and IGZO film, respectively. The distribution of charges in the IGZO layer is dependent on the applied voltage on the gate electrodes. As shown in Fig. 1, the channel layer of DG TFTs is divided into the main and the sub channels. For the conventional single-gate (SG) IGZO TFTs with inverter staggered structure, which has been widely used for decades, the drain-to-source current can only flow through the main channel, which is solely controlled by the bottom gate. However, for DG IGZO TFTs, it is also possible that drain-to-source current flows through the sub channel in the case that the top-gate voltage ($V_{\rm TG}$) is larger than the threshold voltage of TG ($V_{\rm TT0}$). Furthermore, the charge distribution in the main channel will also be affected by the top gate if $V_{\rm TG} < V_{\rm TT0}$, and the threshold voltage will be adjusted accordingly. When $C_{\rm TI}$ and $C_{\rm dep}$ are in serial configuration, the charge in the main channel is influenced by the top gate through $C'_{\rm TI}$, which is approximately expressed as $C'_{\rm TI}=(C_{\rm TI}C_{\rm dep})/(C_{\rm TI}+C_{\rm dep})$.[12]
cpl-35-2-027302-fig1.png
Fig. 1. Simplified cross-sectional view of dual-gate IGZO TFTs.
The drain-source current (i.e., $I_{\rm DS}$) of TFTs is in proportion to the electron velocity of the electron in the channel (i.e., $\mu_{\rm EF}(dV/dy)$, where $\mu_{\rm EF}$ is the effective field effect mobility). Therefore, the voltage drop is expressed as $$\begin{align} dV=\frac{I_{\rm DS} dy}{W\mu _{\rm FE} |Q|},~~ \tag {1} \end{align} $$ where $dV$ is the voltage drop from $y$ to $y+dy$, and $W$ is the channel width. The value of $Q$ represents the gate-induced charges, which can be expressed as[13] $$\begin{align} Q=\,&A[{V_{\rm BG}\! -\!V_{\rm BT0}\! -\!V(y)}]+B[{V_{\rm TG} \!-\!V_{\rm TT0} \!-\!V(y)}],~~ \tag {2} \end{align} $$ $$\begin{align} A=\,&C_{\rm BI} \frac{{\rm sgn}V_{\rm BG} +1}{2}+\frac{C_{\rm BI} C_{\rm dep}}{C_{\rm BI} +C_{\rm dep}}\frac{1-{\rm sgn}V_{\rm BG}}{2},~~ \tag {3} \end{align} $$ $$\begin{align} B=\,&C_{\rm TI} \frac{{\rm sgn}V_{\rm TG} +1}{2}+\frac{C_{\rm TI} C_{\rm dep}}{C_{\rm TI} +C_{\rm dep}}\frac{1-{\rm sgn}V_{\rm TG}}{2},~~ \tag {4} \end{align} $$ where $V_{\rm BT0}$ and $V_{\rm TT0}$ are the threshold voltages of the main and the sub channels, $V_{\rm BG}$ and $V_{\rm TG}$ are the voltages of BG and TG, respectively. The effective field mobility is dependent on gate voltage, and it is expressed as $$\begin{align} \mu _{\rm FE} =\mu _{\rm BAND} ({V_{\rm G} -V_{\rm FB}})^\gamma ,~~ \tag {5} \end{align} $$ where $V_{\rm FB}$ is the flat band voltage, $\mu_{\rm BAND}$ is the flat band mobility, $V_{\rm G}$ is the gate voltage, and $\gamma$ is a material- and temperature-dependent parameter.[14] Synchronous dual-gate mode means that the top gate electrode and the bottom gate electrode are connected (i.e., $V_{\rm BG}=V_{\rm TG}=V_{\rm G}$). Substituting Eq. (2) into Eq. (1), and integrating Eq. (1) from $y=0$ to $y=L$, the on-current is simplified to $$\begin{alignat}{1} I_{\rm DS} =\,&\frac{W}{L}\mu _{\rm FE} ({C_{\rm BI} +C_{\rm TI}})\Big\{\Big[V_{\rm G}\\ &-\frac{({C_{\rm BI} V_{\rm BT0}+C_{\rm TI} V_{\rm TT0}})}{C_{\rm BI} +C_{\rm TI}}\Big]V_{\rm DS} -\frac{1}{2}V_{\rm DS}^2\Big\}.~~ \tag {6} \end{alignat} $$ Here the effective gate capacitance of unit gate insulator area ($C_{\rm DI}$) is the total capacitance of top and bottom gate insulating layers ($C_{\rm BI}$ and $C_{\rm DI}$), $$\begin{align} C_{\rm DI} =C_{\rm BI} +C_{\rm TI},~~ \tag {7} \end{align} $$ and the effective threshold voltage ($V_{\rm DTH}$) is expressed as $$\begin{align} V_{\rm DTH} =\frac{C_{\rm BI} V_{\rm BT0} +C_{\rm TI} V_{\rm TT0}}{C_{\rm BI} +C_{\rm TI}}.~~ \tag {8} \end{align} $$ Thus in the case of $V_{\rm DS}>V_{\rm G}-V_{\rm DTH}$, the drain-to-source current for saturation region is $$\begin{alignat}{1} I_{\rm DS} =\frac{W}{2L}\mu _{\rm FE} C_{\rm DI} ({V_{\rm G} -V_{\rm DTH}})^2({1+\lambda \cdot V_{\rm DS}}),~~ \tag {9} \end{alignat} $$ where $\lambda $ is the kink effect coefficient. For sub-threshold region, $I_{\rm sub}$ is determined by diffusion of gate-to-channel field and it is expressed as[15] $$\begin{align} I_{\rm DS} =\,&I_{\rm DG} \frac{W}{L}[1-e^{-({\ln 10})\frac{\theta _1 V_{\rm DS}}{{\rm SS}_{\rm DG}}}]e^{(\ln 10)\frac{\theta _2 ({V_{\rm G} -V_{\rm FB}})}{{\rm SS}_{\rm DG}}},~~ \tag {10} \end{align} $$ $$\begin{align} {\rm SS}_{\rm DG} =\,&\frac{k_{_{\rm B}} T}{q}({\ln 10})\Big({1+\frac{C_{\rm dep}}{C_{\rm DI}}}\Big),~~ \tag {11} \end{align} $$ where $I_{\rm DG}$ is the drain-source current at $V_{\rm G}=V_{\rm DTH}$, $SS _{\rm DG}$ is the sub-threshold swing of synchronous DG IGZO TFTs, $\theta _{1}$ and $\theta _{2}$ are the fitting parameters. The leakage drain-source current is expressed as $$\begin{align} I_{\rm DS} =G_{\rm DG} V_{\rm DS} \frac{W}{L},~~ \tag {12} \end{align} $$ where $G_{\rm DG}$ is the conductivity coefficient for leakage region. To sum up, using the smoothing function $f(x, y)=[(x^{m}y^{m})/(x^{m}+y^{m})]^{1/m}$ and $\tanh(x)$,[16] the unified model for drain-to-source current of synchronous dual-gate IGZO TFTs can be expressed as $$\begin{align} I_{\rm DS} =\,&\frac{W}{L}\mu _{\rm FE} C_{\rm DI} \frac{({V_{\rm G} -V_{\rm DTH}})}{2}\Big([2V_{\rm DS} ( {V_{\rm G} -V_{\rm DTH}})\\ &-V_{\rm DS}^2]^m\Big\{\Big[2V_{\rm DS} -\frac{V_{\rm DS}^2}{({V_{\rm G} -V_{\rm DTH}})}\Big]^m\\ &\cdot(1+\lambda V_{\rm DS})^{-m}+(V_{\rm G} -V_{\rm DTH})^m\Big\}^{-1}\Big)^{1/m}\\ &\cdot\Big[\frac{1+\tanh [\beta ({V_{\rm G} -V_{\rm DTH}})]}{2}\Big]\\ &+\Big\{I_{\rm DG} \frac{W}{L}[1-e^{-(\ln 10)\frac{\theta _1 V_{\rm DS}}{{\rm SS}_{\rm DG}}}]\\ &\ln [1+e^{\ln (10)\frac{\theta _2 ({V_{\rm G} -V_{\rm FB}})}{{\rm SS}_{\rm DG}}}]+G_{\rm DG} V_{\rm DS} \frac{W}{L}\Big\}\\ &\cdot\Big[\frac{1-\tanh [\beta (V_{\rm G} -V_{\rm DTH})]}{2}\Big],~~ \tag {13} \end{align} $$ where $m$ is the smoothing parameter and $\beta$ is the fitting parameter. Based on the derived current–voltage model, the output and transfer characteristic can be obtained by Hspice simulator incorporating the Verilog-A code. Comparisons between the calculation and the measurement are carried out as shown in Fig. 2.[17] As good agreements are obtained, the above derived analytical model is highly reliable.
cpl-35-2-027302-fig2.png
Fig. 2. Comparison of calculation and measurement electrical characteristic for synchronous dual-gate IGZO TFTs: (a) with output characteristic and (b) with transfer characteristic.
On the other hand, asynchronous dual-gate mode means that the top-gate electrode and the bottom-gate electrodes are biased independently. The IGZO channel is mainly controlled by the bottom gate, and the top gate is only used to adjust the threshold voltage linearly. As listed in Table 1, the thickness of the IGZO layer is much smaller than the bottom- and top-gate insulators. Thus it is reasonable to assume $C_{\rm dep}\gg C_{\rm BI}$ or $C_{\rm TI}$. Then the drain-to-source current behavior for the above threshold region is written as $$\begin{alignat}{1} I_{\rm DS} =\,&\frac{W}{L}\mu _{\rm FE} \Big\{C_{\rm BI} \Big[V_{\rm BG} -V_{\rm BT0} +\frac{C_{\rm TI}}{C_{\rm BI}}(V_{\rm TG}\\ &-V_{\rm TT0})\Big]V_{\rm DS} -\frac{1}{2}(C_{\rm BI} +C_{\rm TI})V_{\rm DS}^2\Big\},~~ \tag {14} \end{alignat} $$ where the threshold voltage of asynchronous DG IGZO TFTs is defined as $$\begin{align} V_{\rm BTH} =V_{\rm BT0} -\frac{C_{\rm TI}}{C_{\rm BI}}(V_{\rm TG} -V_{\rm TT0}).~~ \tag {15} \end{align} $$ In other words, the threshold voltage is linearly decreasing with the increases of the TG voltage, and the coefficient is $C_{\rm TI}/C_{\rm BI}$. Therefore, in the case of $V_{\rm DS}\ge(V_{\rm BG}-V_{\rm BTH})(C_{\rm BI}/C_{\rm DI})$, the saturation current of the device is expressed as $$\begin{align} I_{\rm DS} =\frac{W}{2L}\mu _{\rm FE} \frac{C_{\rm BI}^2}{C_{\rm BI}+C_{\rm TI}}(V_{\rm BG} -V_{\rm BTH})^2(1+\lambda V_{\rm DS}),~~ \tag {16} \end{align} $$ and the sub-threshold current is expressed as $$\begin{align} I_{\rm DS} =\,&I_{\rm BG} \frac{W}{L}e^{(\ln 10)\frac{\theta _2 [{V_{\rm BG} -V_{\rm FB} +\frac{C_{\rm TI}}{C_{\rm BI}}(V_{\rm TG} -V_{TH0})}]}{{\rm SS}_{\rm BG}}}\\ &\cdot[1-e^{-(\ln 10)\frac{\theta _1 V_{\rm DS}}{{\rm SS}_{\rm BG}}}],~~ \tag {17} \end{align} $$ $$\begin{align} {\rm SS}_{\rm BG} =\,&\frac{k_{_{\rm B}} T}{q}(\ln 10)\Big(1+\frac{C_{\rm dep}}{C_{\rm BI}}\Big),~~ \tag {18} \end{align} $$ where $I_{\rm BG}$ is the drain-source current at $V_{\rm BG}=V_{\rm BTH}$, and $SS _{\rm BG}$ is the sub-threshold swing of asynchronous DG IGZO TFTs. Therefore, also using the smoothing function $f(x,y)=[(x^{m}y^{m})/(x^{m}+y^{m})]^{1/m}$, the unified model for drain-to-source current of asynchronous DG IGZO TFTs can be expressed as $$\begin{align} I_{\rm DS} =\,&\frac{W}{L}\mu _{\rm FE} C_{\rm BI} \frac{({V_{\rm BG} -V_{\rm BTH}})}{2}\\ &\cdot\Big(\Big[2\frac{C_{\rm BI}}{C_{\rm BI} +C_{\rm DI}}V_{\rm DS} ({V_{\rm BG} -V_{\rm BTH}})\\ &-V_{\rm DS}^2\Big]^m\Big\{\Big[2V_{\rm DS}-\frac{V_{\rm DS}^2}{C_{\rm BI} ({V_{\rm BG} -V_{\rm BTH}})}\Big]^m\\ &\cdot(1+\lambda V_{\rm DS})^{-m}+\frac{C_{\rm BI}}{C_{\rm BI} +C_{\rm DI}}(V_{\rm BG}\\ &-V_{\rm BTH})^m\Big\}^{-1}\Big)^{\frac{1}{m}}\Big[\frac{1}{2}+\frac{\tanh [\beta ({V_{\rm BG} -V_{\rm BTH}})]}{2}\Big]\\ &+\Big(I_{\rm BG} \frac{W}{L}[1-e^{-(\ln 10)\frac{\theta _1 V_{\rm DS}}{{\rm SS}_{\rm BG}}}]\\ &\cdot\ln \Big\{1+e^{(\ln 10)\frac{\theta _2 [ {V_{\rm BG} -V_{\rm FB} +\frac{C_{\rm TI}}{C_{\rm BI}}(V_{\rm TG} -V_{TH0})}]}{{\rm SS}_{\rm BG}}}\Big\}\\ &+G_{\rm BG} V_{\rm DS} \frac{W}{L}\Big)\Big(\frac{1-\tanh [\beta ({V_{\rm BG} -V_{\rm BTH}})]}{2}\Big).~~ \tag {19} \end{align} $$ Figure 3 shows the calculated transfer characteristic by Hspice simulations incorporating Verilog-A based on the derived model.[18] It is observed that the threshold voltage positively shifts with decreasing the TG voltage for constant sub-threshold swing and off-region current. The increase of threshold voltage is attributed to the depletion of charges in the IGZO film for the negative top-gate voltage. Due to the adjustable threshold voltage, multiple functions can be realized by asynchronous DG IGZO TFTs with increasing flexibility in circuit design. The touch sensing efficiency with SG and DG TFTs is compared.[19] Figure 4(a) shows the touch pixel circuit based on photodiode (PD). The pixel consists of one driving TFT (M1), one capacitance (C1), the switching TFT (M2) and the load capacitance (C2), and the parameters for the investigated pixel are listed in Table 2. As the leakage current is in proportion to the light intensity, the output voltage is increased by the finger-touching events with the decrease of the leakage current through PD. For the conventional structure, M1 is with the single-gate structure. We propose to replace M1 with a dual-gate structure for a higher driving ability. The value of $V_{\rm DD}/V_{\rm B}$ is 6 V, $V_{\rm SS}$ and $V_{\rm SSR}$ are $-$3 V, and $-$6 V, respectively. It is required that the value of $V_{\rm SS}$ is smaller than the threshold voltage of M1. The voltage $V_{\rm TT}$ received by the top-gate electrode is increased from $-$6 V to $V_{\rm TG}$ in the sensing period.
cpl-35-2-027302-fig3.png
Fig. 3. The calculated transfer characteristic of asynchronous dual-gate IGZO TFTs with various $V_{\rm TG}$.
cpl-35-2-027302-fig4.png
Fig. 4. The touch sensor schematic (a), and transient response of touch sensor with single-gate (b), synchronous dual-gate (c), and asynchronous dual-gate (d) IGZO TFTs.
Table 2. The parameters for touch pixel circuit.
Parameter Value
Channel width/length of M1 (μm/μm) 60/10
Channel width/length of M2 (μm/μm) 12/4
$C_{1}$ (pF) 0.2
$C_{2}$ (pF) 25
Figure 4 shows the output of touch-sensing circuit with different M1 structures. For the asynchronous dual-gate mode, the difference of $V_{\rm OUT}$ between dark and light states is 5 V, which is larger than the single-gate and synchronous dual-gate structures. This is attributed to the increase of $V_{\rm OUT}$ for the asynchronous dual-gate mode under the dark condition, as the gate capacitance of M1 is as small as that of the single-gate mode, and the threshold voltage of M1 is comparable with the synchronous dual-gate mode. This is also closely related to the decrease of $V_{\rm OUT}$ for the asynchronous dual-gate mode under the light condition, due to the fast discharging of the gate electrode of M1 whose capacitance is small. In summary, a compact model for drain-to-source current of dual-gate IGZO TFTs is investigated. By integration of the expression of channel charges, which is controlled by gate voltage, unified models for current-to-voltage DG IGZO TFTs with synchronous and asynchronous modes are derived. It is proved that the threshold voltage of asynchronous dual-gate IGZO TFTs is adjusted by top-gate voltage with the coefficient of $C_{\rm TI}/C_{\rm BI}$. By implementing the proposed model with Verilog-A, a touch-sensing circuit using dual-gate structure is investigated. It is found that the touch sensitivity is increased by dual-gate IGZO TFTs. The proposed electrical model for dual-gate IGZO TFTs is promising for promoting realization of system designs on display/touch panels. References Temperature-dependent bias-stress-induced electrical instability of amorphous indium-gallium-zinc-oxide thin-film transistorsElectrical Instability of Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors under Ultraviolet IlluminationChitosan-gated low-voltage transparent indium-free aluminum-doped zinc oxide thin-film transistorsCharacteristics of Double-Gate Ga–In–Zn–O Thin-Film TransistorSolution-processed lithium-doped zinc oxide thin-film transistors at low temperatures between 100 and 300 °CElectrical Properties and Stability of Dual-Gate Coplanar Homojunction DC Sputtered Amorphous Indium–Gallium–Zinc–Oxide Thin-Film Transistors and Its Application to AM-OLEDsOne Gate Diode-Connected Dual-Gate a-IGZO TFT Driven Pixel Circuit for Active Matrix Organic Light-Emitting Diode DisplaysIn-cell capacitive-type touch sensor using LTPS TFT-LCD technologyA Continuous-Grain Silicon-System LCD With Optical Input FunctionAmorphous In–Ga–Zn–O Dual-Gate TFTs: Current–Voltage Characteristics and Electrical Stress InstabilitiesThe Theoretical Electrical Characteristics of Organic Thin Film Transistors Based on Capacitance ModulationA Drain Current Model Based on the Temperature Effect of a-Si:H Thin-Film TransistorsUniversal Compact Model for Thin-Film Transistors and Circuit Simulation for Low-Cost Flexible Large Area ElectronicsUnified Analytic Model for Current–Voltage Behavior in Amorphous Oxide Semiconductor TFTsModeling of current—voltage characteristics for double-gate a-IGZO TFTs and its application to AMLCDsAchieving High Performance Oxide TFT-Based Inverters by Use of Dual-Gate Configurations With Floating and Biased Secondary GatesActive matrix touch sensor detecting time-constant change implemented by dual-gate IGZO TFTs
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