⇦Chinese Physics Letters, 2017, Vol. 34, No. 9, Article code 090601 Direct Digital Frequency Control Based on the Phase Step Change Characteristic between Signals * Zhao-Min Jia(贾兆旻)1,2,4**, Xu-Hai Yang(杨旭海)1,2,3, Bao-Qi Sun(孙保琪)1,2,3, Xiao-Ping Zhou(周晓平)5, Bo Xiang(向波)4, Xin-Yu Dou(窦新宇)4 Affiliations 1National Time Service Centre, Chinese Academy of Sciences, Xi'an 710600 2School of Astronomy and Space Science, University of Chinese Academy of Sciences, Beijing 100049 3Key Laboratory of Precise Positioning and Timing Technology, Chinese Academy of Sciences, Xi'an 710600 4Intelligence and Information Engineering College, Tangshan University, Tangshan 063020 5China Academy of Space Technology (Xi'an), Xi'an 710000 Received 19 June 2017 *Supported by the National Natural Science Foundation of China under Grant No 11173026, and the International GNSS Monitoring and Assessment System (iGMAS) of National Time Service Centre.
**Corresponding author. Email: zhaolianhanhan@126.com Citation Text: Jia Z M, Yang X H, Sun B Q, Zhou X P and Xiang B et al 2017 Chin. Phys. Lett. 34 090601 Abstract We present a new digital phase lock technology to achieve the frequency control and transformation through high precision multi-cycle group synchronization between signals without the frequency transformation circuit. In the case of digital sampling, the passing zero point of the phase of the controlled signal has the phase step characteristic, the phase step of the passing zero point is monotonic continuous with high resolution in the phase lock process, and using the border effect of digital fuzzy area, the gate can synchronize with the two signals, the quantization error is reduced. This technique is quite different from the existing methods of frequency transformation and frequency synthesis, the phase change characteristic between the periodic signals with different nominal is used. The phase change has the periodic phenomenon, and it has the high resolution step value. With the application of the physical law, the noise is reduced because of simplifying frequency transformation circuits, and the phase is locked with high precision. The regular phase change between frequency signals is only used for frequency measurement, and the change has evident randomness, but this randomness is greatly reduced in frequency control, and the certainty of the process result is clear. The experiment shows that the short term frequency stability can reach 10$^{-12}$/s orders of magnitude. DOI:10.1088/0256-307X/34/9/090601 PACS:06.30.Ft, 06.20.Dk, 07.05.Fb, 07.50.Qx © 2017 Chinese Physics Society Article Text Two frequency signals need to have the same nominal in traditional phase locked systems, and numerous frequency conversion circuits have been used, thus the system is complicated and the measurement precision is reduced with the additional noise.[1-3] In a high precision test system, precision of the signal frequency must be higher, and the high resolution time-frequency processing technology is very important.[4,5] Phase difference period shift plays a significant role in the time and frequency domains, and it shows a kind of quantization relation.[6] Based on the regularity change theory of the phase difference group, there is a high precision character of phase difference change between different nominal signals.[7,8] In analog circuits, the phase difference change becomes complex when the relationship between the signals is very complex, and the detection circuit stability decreases. The features such as least common multiple period, the phase step change and the border effect of fuzzy area are not dependent on the analog circuits, these features can also be used in the direct digital frequency control system. The system is quite different from the existing methods of frequency transformation and frequency synthesis, it simplifies the circuit structure, and achieves the good stability index. In Fig. 1, $f_{2}$ is the frequency value of the controlled signal, $f_{1}$ is the frequency value of the clock signal, which are of the two frequency signals. There is a greatest common factor frequency $f_{\rm maxc}$ between the two signals, $f_{1}=Af_{\rm maxc}$, $f_{2}=Bf_{\rm maxc}$, and the least common multiple period $T_{\rm minc}$ is equal to $1/f_{\rm maxc}$.[9]
cpl-34-9-090601-fig1.png
Fig. 1. The periodic character of digital sampling.
The passing zero point of the sampled signal is considered as the feature point, and the passing zero point will be repeated after each $T_{\rm minc}$ time. The periodic characteristic of the passing zero point is determined by the relationship between the two frequency signals, if the passing zero points are used as the gate switch, then the gate can synchronize with the two signals. In a $T_{\rm minc}$ time, the relationship between the two signals is expressed as $$\begin{align} T_{\min c} =\frac{A}{f_1}=\frac{B}{f_2},~~ \tag {1} \end{align} $$ where $A$ is the period number of the sampling clock signal in a $T_{\rm minc}$ time, and $B$ is the period number of the controlled signal. According to the change characteristic of the phase difference group, the phase difference change has the group consecutive character and the high precision step character. When $f_{2}$ has a slight deviation $\Delta f$, the passing zero point will change with a step $\Delta T$ for each $T_{\rm minc}$ time,[10] and the point will become the original value back after a group period time, $$\begin{align} \Delta T=\frac{f'_{\max c}}{(f_2 +\Delta f)\times f_1},~~ \tag {2} \end{align} $$ where $f_{\rm maxc}$ is the greatest common factor frequency between $(f_{2}+\Delta f)$ and $f_{1}$. The digital value change of the passing zero point contains the information of the step value $\Delta T$, which reflects the high precision phase change of the controlled signal. Using the phase change information, the digital phase locked system can simplify the complex frequency conversion circuit, and the frequency can be controlled with high precision.
cpl-34-9-090601-fig2.png
Fig. 2. The block diagram of the digital direct frequency control system.
cpl-34-9-090601-fig3.png
Fig. 3. The soft flow of data process.
The digital direct frequency control system is shown in Fig. 2. The value of the A/D clock signal is $f_{1}$. The controlled signal is sampled with the clock signal. The sampled data is processed and operated by FPGA. A control voltage value will be outputted each operation time. The VCOCXO will not be adjusted with $U_{\rm c}$ outputted by the D/A, until the phase of the passing zero point does not change with time, the phase is locked, and the controlled signal achieves the target value. The soft flow of data process is shown in Fig. 3. In coarse control, using the least common multiple period, the integral period of the controlled signal can be measured in the short gate time. In fine control, the non-integral period of the controlled signal can be corrected with the digital voltage of the passing zero point in the gate time, then the gate synchronizes with the two signals, and the control precision is improved.
cpl-34-9-090601-fig4.png
Fig. 4. The relationship between the gate and the two signals.
The relationship between the gate and the two signals is shown in Fig. 4. The phase step $\Delta T$ of the passing zero point has extremely high resolution, for example, $f_{1}$ of the sampling clock signal is 20 MHz, the target value $f_{2}$ of the controlled frequency signal is 5 MHz, the deviation $\Delta f$ is 1 Hz, and $\Delta T$ is 0.01 ps. Such high phase resolution reflects the advantage of digital phase locked system, but the resolution of the A/D converter needs to be fully considered. The resolution, which directly leads to measurement error, is considered to be the decisive factor affecting the measurement precision, especially under the condition of super-high resolution digital measurement.[11,12] Assuming that the conversion digit is 16, the peak of the controlled frequency signal is $U_{m}$, the voltage resolution of the A/D converter is $U_{m}/2^{16}$, which is about 1.5259$\times10^{-5}U_{m}$, the voltage change value corresponding to $\Delta T$ is $U_{m}\sin(2\pi\times 10\,{\rm MHz}\times0.01\,{\rm ps})$, which is about 6.2832$\times10^{-7}U_{m}$. Therefore, the ultra fine phase change cannot obtain a digital voltage value after each $T_{\rm minc}$ time. That is, there are $m$ phase changes that will obtain the same digital voltage $U_{1}$. When the difference between $U_{1}$ and $U_{2}$ corresponding to the $(m+1)$ phase change is greater than the converter resolution, the sampled voltage value will jump from $U_{1}$ to $U_{2}$, and there are some phase changes that will obtain the same digital voltage $U_{2}$ after $U_{1}$, and so on, a set of digital fuzzy areas is created. To reduce the influence of the digital fuzzy area, the border effect theory is used. The time on which $U_{n}$ jumps to $U_{1}$ is used as the switch time of the gate, that is, taking the border of the fuzzy area as the switch, the stability of the border reflects the ultra fine phase difference change. It gets rid of the restriction of the converter resolution,[13,14] and then the phase locked function with high accuracy is completed. The preset gate does not synchronize with the two signals $\Delta t_{1}$ and $\Delta t_{2}$, and there is a synchronization error. The synchronization error is corrected by the real gate switch, which is generated when the digital voltage jumps from $U_{1}$ to $U_{2}$ stably, then the quantization error is eliminated, the high resolution measurement is guaranteed. In coarse control, the short gate time, in which the controlled signal is adjusted coarsely, is set to the fast response, then the passing zero point has the fine step change, with which the non-integral period of the controlled signal is corrected, and the gate synchronizes with the two signals, the phase is locked with high precision. In the process of frequency control, the period number $A'$ of the sampling clock signal and the period number $B'$ of the controlled signal are counted in the gate. The relationship between the two signals can be expressed as $$\begin{align} \tau =\frac{{B}'}{(f_2 +\Delta f)}=\frac{{A}'}{f_1}.~~ \tag {3} \end{align} $$ The controlled frequency value is $$\begin{align} (f_2 +\Delta f)=\frac{{B}'}{{A}'}\times f_1.~~ \tag {4} \end{align} $$ The target value of the controlled frequency signal is $$\begin{align} f_2 =\frac{B}{A}\times f_1.~~ \tag {5} \end{align} $$ According to Eqs. (3) and (4), the deviation value $\Delta f$ is $$\begin{align} \Delta f=\Big(\frac{{B}'}{{A}'}-\frac{B}{A}\Big)\times f_1.~~ \tag {6} \end{align} $$ The phase change of the passing zero point in the phase lock process is shown in Fig. 5. When the phase is not locked, the phase of the passing zero point changes with the step $\Delta T$ for every $T_{\rm minc}$ time, such as $a$, $b$ and $c$. Through the digital sampling, the stable digital border is generated by the step change to make the gate synchronize with the two signals, then the period number is measured with high precision, and the phase of the passing zero point does not change, such as $a'$, $b'$ and $c'$, the controlled signal reaches the target value. For example, the frequency value $f_{1}$ of the sampling clock signal is 10.23 MHz, the target value $f_{2}$ of the controlled frequency signal is 10 MHz, and $T_{\rm minc}$ is 0.1 ms, in which the period numbers of the two signals are counted, the calculation value of $A/B$ is 1.023. When there is a deviation value $\Delta f$, $A/B$ is not 1.023. If $A/B$ is greater than 1.023, the voltage $U_{\rm c}$ must be reduced accordingly, and if $A/B$ is less than 1.023, the voltage $U_{\rm c}$ must be increased accordingly. When the actual ratio is 1.023, the coarse control is completed. The non-integral period of the controlled signal is corrected in the gate time by analyzing the digital voltage value of the phase zero point, then the gate synchronizes with the two signals, and the phase of the passing zero point is locked with high precision.
cpl-34-9-090601-fig5.png
Fig. 5. The phase change of the passing zero point in the phase lock process.
The experiment is shown in Fig. 6, the frequency $f_{1}$ of the signal synthesized by HP8662A is 10.23 MHz, the controlled frequency $f_{2}$ of the VCOCXO is 10 MHz, and the synthesized signal is taken as the clock signal of A/D. The controlled signal is sampled by the digital direct phase lock system. The sample data is analyzed and processed, then the control voltage $U_{\rm c}$ is outputted to control VCOCXO, the controlled signal reaches the target value, and then the frequency stability is measured.
cpl-34-9-090601-fig6.png
Fig. 6. The experimental block diagram.
The experimental result is listed in Table 1. The frequency stability is calculated with the Allan variance formula.[15] The nominal of the clock signal is different from the controlled frequency signal, the relationship has a certain complexity, and the frequency stability can reach 10$^{-12}$ per second. With the time extension, the frequency stability can reach 10$^{-13}$ per thousand seconds.
Table 1. The frequency stability.
$\sigma$/s Frequency stability
1 6.72$\times$10$^{-12}$
4 2.53$\times$10$^{-12}$
16 1.62$\times$10$^{-12}$
64 8.93$\times$10$^{-13}$
256 6.63$\times$10$^{-13}$
1024 1.87$\times$10$^{-13}$
Compared with the traditional phase locked circuit, the phase can be locked directly in the digital phase locked system when the nominal frequency is different. It simplifies the circuit, and reduces the noise, and the stability is improved. In the experiment, $f_{\rm maxc}$ is 10 kHz, and $T_{\rm minc}$ is 0.1 ms. The frequency correction effect can be judged every 0.1 ms in the phase locked system, and the response time is short. Traditional frequency synthesizer is difficult to have fine frequency adjust step. To have a wide range of frequency modulation, the phase accumulator needs to have larger digits for a high frequency resolution in DDS, but in phase amplitude transformation, the requirement of memory ROM will be very high, and the cost and the power consumption of the system is high. Normally, the high digits of the phase are only captured as the ROM addressing digits in DDS, while the phase truncation error exists, which is the main factor causing DDS spurious. This new frequency control technology is appropriate for the frequency transformation and frequency control in navigation and communication, such as 10.23 MHz, 12.8 MHz and 16.384 MHz. These frequency signals can form the small least common multiple periodic value, the coarse measurement can be completed in a short time gate, and it is not difficult to match the phase step value of these frequency signals with the resolution of the A/D converter. According to the phase change characteristic between the frequency signals, the use of the frequency conversion is reduced effectively. With the increase of the digit number of complex frequency value, the least common multiple periodic value is larger, and the phase step value is complicated. The coarse measurement is difficult to complete in a short time gate, and the synchronous precision of the gate with frequency signals is affected, then the difficulty in frequency control increases. In the direct digital frequency control system, the phase step of the passing zero point is of continuity with high resolution in the measuring process. The quantization error is eliminated, and the short term frequency stability can reach 10$^{-12}$/s orders of magnitude. Numerous frequency transformation circuits are simplified in the direct phase locked system, the gate time can be short to implement a rapid response, and the phase can be locked with high precision by correcting the non-integral period of the controlled signal. The measurement between arbitrary periodic signals is important in time and frequency domains, such as atomic clock frequency signal processing chain, time and frequency transfer.[16] The digital frequency control system provides a new phase lock method, which is of great significance for research of the frequency link and the frequency transformation. References High-precision measurement of the atomic mass of the electronA Novel Super-High Resolution Phase Comparison ApproachA super-high resolution frequency standard measuring approach based on phase coincidence characteristics between signalsStandards of Time and Frequency at the Outset of the 21st CenturySuper-resolution biomolecular crystallography with low-resolution dataPhase Comparison of High-Current Shunts up to 100 kHzApplication of length vernier in phase coincidence detection and precision frequency measurementAn Ultra-Miniature Cell-Type Rb Atomic Clock Based on a Novel Waveguide CavityResearch and application of regular phenomenon between periodic signalsA Portable High-Resolution Surface Measurement DeviceA High-Resolution Ultrasonic Distance Measurement System Using Vernier Caliper Phase MeterVerification and Application of the Border Effect in Precision MeasurementOn precise phase difference measurement approach using border stability of detection resolutionApplication of the Dynamic Allan Variance for the Characterization of Space Clock BehaviorEntanglement-assisted atomic clock beyond the projection noise limit
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