⇦Chinese Physics Letters, 2017, Vol. 34, No. 7, Article code 078502 Hetero-Epitaxy and Self-Adaptive Stressor Based on Freestanding Fin for the 10 nm Node and Beyond * Guang-Xing Wan(万光星)1,2, Gui-Lei Wang(王桂磊)1,2**, Hui-Long Zhu(朱慧珑)1,2** Affiliations 1Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029 2University of Chinese Academy of Sciences, Beijing 100049 Received 9 April 2017 *Supported by the National Key Research and Development Program of China (2016YFA0301701), and the Youth Innovation Promotion Association of CAS under Grant No 2016112 .
**Corresponding author. Email: zhuhuilong@ime.ac.cn; wangguilei@ime.ac.cn Citation Text: Wan G X, Wang G L and Zhu H L 2017 Chin. Phys. Lett. 34 078502 Abstract A promising technology named epitaxy on nano-scale freestanding fin (ENFF) is firstly proposed for hetero-epitaxy. This technology can effectively release total strain energy and then can reduce the probability of generating mismatch dislocations. Based on the calculation, dislocation defects can be eliminated completely when the thickness of the Si freestanding fin is less than 10 nm for the epitaxial Ge layer. In addition, this proposed ENFF process can provide sufficient uniaxial stress for the epitaxy layer, which can be the major stressor for the SiGe or Ge channel fin field-effect transistor or nanowire at the 10 nm node and beyond. According to the results of technology computer-aided design simulation, nanowires integrated with ENFF show excellent electrical performance for uniaxial stress and band offset. The ENFF process is compatible with the state of the art mainstream technology, which has a good potential for future applications. DOI:10.1088/0256-307X/34/7/078502 PACS:85.40.-e, 81.15.-z, 85.40.Bh, 85.30.Tv © 2017 Chinese Physics Society Article Text With the continuous down-scaling of transistor device dimensions, improvements in the Si complementary metal oxide semiconductor (CMOS) technology are rapidly becoming increasingly difficult and expensive.[1] As alternative channel materials, the SiGe, Ge and III–V materials have received significant attention for the upcoming CMOS technology nodes, due to their higher carrier mobilities than that in Si.[2-4] Therefore, it is crucial to find methods to integrate high-quality new materials with the established Si technology in an economically viable way. One of the major challenges for SiGe, Ge and III–V integration on Si is the formation of dislocation defects in the films due to large lattice-mismatch.[5] At present, among the ways to form SiGe or the Ge layer on wafer, ultrathin body SiGe-on-insulator/Ge-on-insulator (SGOI/GOI) structures formed by the Ge condensation technique are most promising for the advanced CMOS logic devices.[6] However, during the condensation process, when the strain is going very high, it starts to be relaxed by generating dislocations, which has not been sufficiently eliminated yet.[7,8] As the theory of epitaxy on a finite substrate,[9,10] when epitaxial layers are grown on nano-scale substrates, strain energy will be released partially and less dislocation be formed, which is the potential for new hetero-materials integration. On the other hand, the effective stressor will be another problem for Ge-channel metal-oxide-semiconductor field-effect transistors (MOSFETs).[11] The performance of relaxed SiGe or Ge channel fin field-effect transistors (FinFETs) is worse than strained Si, which indicates that the stressor is essential for future process nodes. However, the migration of electrons in FinFETs and gate-pitch scaling reduce the effectiveness of the source/drain (S/D) stressor.[12,13] Therefore, a strain-relaxed buffer (SRB) is introduced to offer further mobility enhancement, which is scalable to futures nodes.[14] To integrate the large lattice-mismatch materials on a silicon substrate, we propose a method called epitaxy on a nano-scale freestanding fin (ENFF), which is based on the FinFET technology.[15] The nano-scaled freestanding fin acts as the substrate in the ENFF method, which can effectively release the total strain energy and can reduce the probability of generating misfit dislocations. Meanwhile, the freestanding fin acts as the SRB layer, and provides uniaxial compressive stress and band offset for the epitaxial layer, which enhances hole mobility and is immune to short channel effects (SCEs).[16] In this Letter, the process flow and theoretical discussion based on the SiGe alloy system is presented. In addition, the nanowire-FET based on the ENFF method is simulated by technology computer-aided design (TCAD) and shows good potential for future applications. Figure 1(a) shows the process flow of the ENFF method, which is compatible with the state of the art mainstream technology. The epitaxy of SiGe/Si layers is performed on an 8-inch Si substrate. Then the fin structure is patterned by sidewall image transfer. After the formation of hold structure, the SiGe sacrificial layer will be released by wet etch. Then, the 2nd Si$_{1-x}$Ge$_{x}$ selective epitaxy is performed on the freestanding fin like S/D engineering,[17] which is the wanted channel material. Figure 1(b) shows the final ideal structure and the sizes of freestanding fin and the 2nd epitaxy layer. It is assumed that the type of epitaxy is isotropic for simplicity.
cpl-34-7-078502-fig1.png
Fig. 1. (a) The process flow of ENFF, and (b) the final ideal structure of ENFF.
Because the length and height of the freestanding fin are much larger than the thickness of the epitaxial layer, it is assumed that the strain release effect along the height and length of the fin is ignored. On account of the symmetry, the thickness of the virtual Si substrate is equivalent to $W_{\rm Fin}$/2. According to the theory of epitaxy on a finite substrate, it can be obtained that the total elastic strain energy per area reads $$\begin{align} E_{\rm s} =B_1 f_0^2 h_1 /\lambda _1^2 +B_2 f_0^2 W_{\rm Fin} /2\lambda _2^2,~~ \tag {1} \end{align} $$ where $f_{0}$ is the misfit between the Si$_{1-x}$Ge$_{x}$ epitaxial layer and silicon, $\lambda$ is the factor of reduction in the effective strain for finite substrate, $\lambda _1 =1+B_1 h_1 a_1^2 /B_2 (W_{\rm Fin} /2)a_2^2$, $\lambda _{2}$ has the similar expression, $h_{1}$ is the thickness of the epitaxial layer, and $x$ is the germanium mole fraction. In the ENFF method, owing to the freestanding fin silicon surrounded by the epitaxial layer, there is only one free surface in the epitaxial layer. It can be obtained that the dislocation energy per unit area is $$\begin{align} E_{\rm dis}=\Big(\frac{C_0}{\sqrt 2 a(x)}\Big){\rm ln}(h_1 /b),~~ \tag {2} \end{align} $$ where $C_{0}$ is the constant, $a(x)$ is the lattice constant of Si$_{1-x}$Ge$_{x}$, and $b$ is the magnitude of Burger's vector. Figure 2 shows the relation between $E_{\rm s}$ and $E_{\rm dis}$ with $W_{\rm Fin}=10$ nm and $x=1$, which means that the material of the epitaxial layer is pure germanium. The elastic strain energy is always less than the dislocation energy, which indicates that a Ge layer of any thickness can be grown without generating misfit dislocations. It proves that the ENFF method can effectively release the total strain energy and has the potential to solve the lattice mismatch problem.
cpl-34-7-078502-fig2.png
Fig. 2. Comparison of elastic strain energy and dislocation energy with different thicknesses of epitaxial layers.
cpl-34-7-078502-fig3.png
Fig. 3. (a) The relationships of $y$ and the area ratio $m$, and of stress and the area ratio $m$ with $x=1$. (b) The relationship between stress and germanium mole fraction $x$ with $m=1$.
When the epitaxial layer of lattice constant $a_{1}$ grows on a nano-scaled substrate, $a_{2}$ is brought together in close proximity at thermal equilibrium; they will reach a common lattice constant $a_{0}$ and experience a misfit as if they are situated on a 'virtual' substrate of a lattice constant $a_{0}$. For the ENFF method, the total elastic strain energy per length is $$\begin{align} E_{\rm sall} =E_1 +E_2 =B_1 S_1 f_1^2 +B_2 S_2 f_2^2,~~ \tag {3} \end{align} $$ where $S_{1}$ is the cross sectional area of the epilayer, and $f_{1}$ is the misfit between the epilayer and the 'virtual' substrate. At thermal equilibrium, the total elastic strain energy of the bilayer structure will be minimized, $$\begin{align} \frac{\partial E_{\rm sall} }{\partial a_0 }=0.~~ \tag {4} \end{align} $$ Thus the common lattice constant $a_{0}$ is given by $$\begin{alignat}{1} a_0=\frac{B_1 S_1 a_1^2 +B_2 S_2 a_2^2 }{B_1 S_1 a_1 +B_2 S_2 a_2 }=\frac{B_1 a_1^2 +mB_2 a_2^2 }{B_1 a_1 +mB_2 a_2 },~~ \tag {5} \end{alignat} $$ where $m$ is the area ratio of the epitaxial layer to substrate, which is introduced to ignore the influence of the shape. The 'virtual' substrate just likes the Si$_{1-y}$Ge$_{y}$ SRB with lattice constant $a_{0}$, which offers the epitaxial layer Si$_{1-x}$Ge$_{x}$ compressive stress. Figure 3(a) shows the relationships of $y$ and the area ratio $m$, and of stress and the area ratio $m$, when the material of the epitaxial layer is germanium. It is shown that with the growth of the epitaxial layer, the stress becomes less. Therefore, an appropriate $m$ should be chosen to obtain effective compressive stress for hole mobility enhancement. Figure 3(b) shows the relationship between stress and germanium mole fraction $x$ with $m=1$. It is shown that with the increase of germanium mole fraction, the stress becomes larger. It is noticed that even when $m=1$ and $x=0.4$, the compressive stress reaches 1.7 GPa, which is effective for hole mobility enhancement.
cpl-34-7-078502-fig4.png
Fig. 4. The experimental ENFF structure: (a) the top view, (b) the cross section along AA$'$ by a scanning electron microscope (SEM) and (c) the hexagonal epitaxial layer by a transmission electron microscope (TEM).
According to the process flow in Fig. 1(a), it is found that the baking process in the epitaxy can change the shape of the freestanding fin from a rectangle to a circle. As shown in Fig. 4, the hexagonal epitaxial layer is formed owing to the different growth rates on different crystal faces. The total width of the nanowire is about 31 nm, which can be further optimized to meet the requirements of the fin pitch in volume production. To study the performance of MOSFET devices by the ENFF method, nanowire devices with the same shape in the experiments are simulated by TCAD. Figure 5(a) shows the simulation structure, where the radius of freestanding fin (Si), i.e., FF(Si), is 10 nm, the side length of the hexagonal epitaxial layer (Si$_{0.6}$Ge$_{0.4}$) is 15 nm, and $L_{\rm g}=30$ nm. It is noticed that the maximal width of channel is equal to 30 nm, which is too large for good gate control, and there is no S/D stressor in the simulation. However, as shown in Fig. 5(b), the $I_{\rm d}$–$V_{\rm g}$ curves for linear and saturation modes with $V_{\rm dd}=-0.8$ V show excellent SCE control and super performance, subthreshold swing 65 mV/dec, drain induced barrier lowering (DIBL) 21 mV and $I_{\rm on}$=2100 μA/μm with $I_{\rm off}=100$ nA/μm. The high performance is owing to the uniaxial compressive stress by FF(Si), as in the previous discussion. However, the excellent SCE and leakage control is owing to the different band structures between Si and SiGe.
cpl-34-7-078502-fig5.png
Fig. 5. (a) The simulation structure of the ENFF nanowire. (b) The $I_{\rm d}$–$V_{\rm g}$ curves for linear and saturation modes with $V_{\rm dd}=-0.8$ V.
cpl-34-7-078502-fig6.png
Fig. 6. (a) The profile of current density at the ON-state. (b) The profile of current density at OFF-state. (c) The bandgap along the white line in (a). (d) The band structure of the channel at ON-state.
Figures 6(a) and 6(b) show the profile of current density at ON-state and OFF-state, respectively. It is observed that the current mostly focuses on the SiGe epitaxial layer, which contributes to the good SCE and current leakage control. Figure 6(c) shows the bandgaps of Si and SiGe along the white line in Fig. 6(a). The difference in germanium mole fraction results in the different bandgaps of Si and SiGe. Figure 6(d) shows the conduction and valence bands at ON-state. The band offset between Si and SiGe acts as a quantum-barrier, which confines the carriers in the SiGe layer rather than the Si layer. In summary, the method of epitaxy on the nano-scale freestanding fin (ENFF) can release the strain energy of an epitaxial layer and can eliminate the generation of misfit dislocation at appropriate sizes, which is meaningful to integrate high-quality hetero channel materials with the established Si technology. In addition, this method can provide uniaxial compressive stress for the epitaxy layer, which enhances the hole mobility remarkably. In addition to a mobility boost, the ENFF method shows good SCE and current leakage control for the band offset between Si and SiGe. Moreover, the ENFF process can solve the lattice mismatch and stressor problems for new material integration simultaneously, which has good potential for future applications. References Defects in epitaxial multilayersThe Ge condensation technique: A solution for planar SOI/GeOI co-integration for advanced CMOS technologies?Stacking fault generation during relaxation of silicon germanium on insulator layers obtained by the Ge condensation techniqueIII?V/Ge channel MOS device technologies in nano CMOS eraNew approach to the high quality epitaxial growth of lattice?mismatched materialsTheory of Strain Relaxation for Epitaxial Layers Grown on Substrate of a Finite Dimension7-nm FinFET CMOS Design Enabled by Stress Engineering Using Si, Ge, and SnEffectiveness of Stressors in Aggressively Scaled FinFETsIntegration of highly-strained SiGe materials in 14nm and beyond nodes FinFET technologyOptimization of SiGe selective epitaxy for source/drain engineering in 22?nm node complementary metal-oxide semiconductor (CMOS)
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