⇦Chinese Physics Letters, 2017, Vol. 34, No. 7, Article code 078501 Experimental $I$–$V$ and $C$–$V$ Analysis of Schottky-Barrier Metal-Oxide-Semiconductor Field Effect Transistors with Epitaxial NiSi$_{2}$ Contacts and Dopant Segregation * Yi-Ze Wang(王翼泽)1,5, Chang Liu(刘畅)1,2, Jian-Hui Cai(蔡剑辉)1,3, Qiang Liu(刘强)1,3, Xin-Ke Liu(刘新科)4, Wen-Jie Yu(俞文杰)1**, Qing-Tai Zhao(赵清太)2 Affiliations 1State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050 2Peter Grünberg Institute 9, JARA-FIT, Forschungszentrum Jülich, Jülich 52425, Germany 3College of Sciences, Shanghai University, Shanghai 200444 4College of Materials Science and Engineering, Shenzhen University, Shenzhen 518060 5University of Chinese Academy of Sciences, Beijing 100049 Received 8 March 2017 *Supported by the National Natural Science Foundation of China under Grant No 61674161, and the Open Project of State Key Laboratory of Functional Materials for Informatics.
**Corresponding author. Email: casan@mail.sim.ac.cn Citation Text: Wang Y Z, Liu C, Cai J H, Liu Q and Liu X K et al 2017 Chin. Phys. Lett. 34 078501 Abstract We present an experimental analysis of Schottky-barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) fabricated on ultrathin body silicon-on-insulator substrates with a steep junction by the dopant implantation into the silicide process. The subthreshold swing of such SB-MOSFETs reaches 69 mV/dec. Emphasis is placed on the capacitance-voltage analysis of p-type SB-MOSFETs. According to the measurements of gate-to-source capacitance $C_{\rm gs}$ with respect to $V_{\rm gs}$ at various $V_{\rm ds}$, we find that a maximum occurs at the accumulation regime due to the most imbalanced charge distribution along the channel. At each $C_{\rm gs}$ peak, the difference between $V_{\rm gs}$ and $V_{\rm ds}$ is equal to the Schottky barrier height (SBH) for NiSi$_{2}$ on highly doped silicon, which indicates that the critical condition of channel pinching off is related with SBH for source/drain on channel. The SBH for NiSi$_{2}$ on highly doped silicon can affect the pinch-off voltage and the saturation current of SB-MOSFETs. DOI:10.1088/0256-307X/34/7/078501 PACS:85.30.-z, 73.30.+y, 61.72.uf © 2017 Chinese Physics Society Article Text Schottky-barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) with metallic contacts are expected to have lower parasitic source/drain (S/D) resistances.[1] Since it is easy to form with a silicon compatible process, silicide has been used as an alternative of doped S/D junctions.[2-11] NiSi has been widely employed for SB-MOSFETs.[12-18] However, thicker NiSi contacts at S/D cause large encroachment of NiSi into the channel due to the fast diffusion of Ni in Si, which hinders down scaling of SB-MOSFETs. Ultrathin silicides may be a solution as they show greatly improved line edge uniformity.[19] Furthermore, epitaxial silicides, which form atomically flat silicide/silicon (111) aligned interfaces along $\langle110\rangle$ directions even over a few micrometers, provide uniform contacts at S/D.[20] The performance of SB-MOSFETs is strongly dependent on the Schottky barrier height (SBH). A large SBH degrades the device performance resulting in low on-current, poor subthreshold swings and ambipolar switching. Therefore, low SBHs should be used to improve the device performance. SBH amounting to 0.65 eV for NiSi on n-Si and 0.35 eV for epitaxial NiSi$_{2}$ were achieved experimentally.[21-24] To reduce the effective SBH, dopant segregation (DS) at source and drain were applied.[25-31] The scaling behavior and improved properties of SB-MOSFETs caused by dopant segregation using the implantation into the silicide (IIS) method have been characterized.[32,33] However, the impact of dopant segregation on the capacitance of SB-MOSFET is still missing and unclear. In this Letter, we present the experimental results of long channel SB-MOSFETs on ultra-thin body silicon-on-insulator (SOI) substrates with boron segregation using the IIS method. Particular emphasis is placed on the capacitance-voltage ($C$–$V$) characterization of devices. The gate-to-source capacitance $C_{\rm gs}$ and gate-to-drain capacitance $C_{\rm gd}$ with respect to $V_{\rm gs}$ at different frequencies and various $V_{\rm ds}$ are measured and analyzed. In experiment, the SB-MOSFETs were fabricated on 20-nm-thick SOI substrates with a 145 nm buried oxide (BOX) layer. The schematic device structure and main process steps are shown in Fig. 1(a). After mesa isolation and RCA cleaning, a 5-nm-thick HfO$_{2}$ layer as gate dielectric was grown by atomic layer deposition (ALD), followed by atomic vapor deposition (AVD) of 60 nm TiN as the metal gate. The gate was defined with the length varied from 11 μm to 3 μm by optical lithography. The UV6$^{\rm TM}$ positive DUV photoresist was used in the photolithography process. The photoresist was spin coated on the sample at a rotation speed of 4000 rpm, thus the thickness of the photoresist was about 1 μm. The exposure intensity was 3.8 mW/cm$^{2}$ and the exposure duration is 5.6 s. The exposed portion of the photoresist was dissolved in the Megaposit MF24A Developer for 45 s. The exposed area was etched back to the silicon using dry and wet etching. After gate patterning, an ultrathin Ni layer of about 2.7 nm was deposited by sputtering on the clean and oxide-free Si surface. Silicidation was performed in forming gas (N$_{2}$/H$_{2}$) at 700$^{\circ}\!$C for 30 s to form single crystalline NiSi$_{2}$,[19] while the excessive Ni was removed by a selective wet etching in diluted H$_{2}$SO$_{4}$. After silicidation, boron ions were implanted into source and drain at 1.5 keV to a dose of $2\times10^{15}$ cm$^{-2}$ with the angle of 45$^{\circ}$ and 135$^{\circ}$, respectively. During a short rapid thermal annealing (RTA) at 500$^{\circ}\!$C for 10 s boron dopants diffuse to the silicide/silicon interface, generating a steep source/channel and drain/channel junction by DS. Finally, a 5 nm adhesion layer Cr followed by 150 nm Pt was deposited as metal contacts for the source, drain and gate. The microstructure of the fabricated device was characterized by a cross-sectional transmission electron microscope (TEM). The TEM image of the source/channel junction, as shown in Fig. 1(b), indicates good gate alignment without encroachment of silicide into the channel region. Figure 1(c) shows the TEM image of the semiconductor/insulator interface. The uniform and flat Si/HfO$_{2}$ interface layer reveals the good interface quality.
cpl-34-7-078501-fig1.png
Fig. 1. (a) The schematic structure and main process flow of the fabricated SB-MOSFETs. (b) TEM cross-sectional image of source/channel junction. Ultrathin Ni layer deposited and single crystalline NiSi$_{2}$ was formed by silicidation with no encroachment into the channel region. (c) TEM image of the semiconductor/insulator interface showing the good interface quality.
The schematic band diagram of an SB-MOSFET with and without boron segregation is shown in Fig. 2. The band of the channel bends upward strongly at the interfaces of silicon and silicide due to the highly boron doped segregation pocket. The Schottky barrier of p-type silicon and silicide became much thinner and the effective SBH for holes was lower than that of intrinsic silicon and silicide junction. Thus the extremely thin SB is almost transparent to the carriers, and the device behaves as a conventional MOSFET. Due to the different band bendings between the devices with and without DS as shown in Figs. 2(a) and 2(b), the ambipolar behavior is significantly suppressed. For example, when $V_{\rm gs}$ is positive, electrons inject into the conduction band by tunneling through the Schottky barrier at the drain contact, resulting in a much less electron current because of a higher barrier in the DS case (as shown by the green arrow in the figure). Reducing $V_{\rm gs}$ to values in the subthreshold regime, the injection of electrons from the drain is suppressed and the injection of holes from the source by thermionic emission is enabled. Thus the subthreshold slope in this regime is close to the thermal limit of 60 mV per decade. With a further decrease of negative $V_{\rm gs}$, holes inject into the valance band by tunneling through the Schottky barrier at the source contact, resulting in a much higher holes current because of a thinner barrier in the DS case (as shown by the red arrow in the figure).
cpl-34-7-078501-fig2.png
Fig. 2. Schematic views of (a) the band diagram of an SB-MOSFET at different gate-voltages without DS. (b) The band diagram of fabricated SB-MOSFET at different gate-voltages with DS. The highly boron doped segregation pockets at S/D lead to a strong upward band bending at the silicon/silicide interface. The effective SBH for electrons at the drain becomes higher while for holes at the source it becomes lower.
cpl-34-7-078501-fig3.png
Fig. 3. Transfer characteristics of 3μm-gate SB-MOSFET at room temperature with different $V_{\rm ds}$, showing an SS = 69 mV/dec and a high $I_{\rm on}/I_{\rm off}$ ratio $\sim$10$^{8}$. The output characteristics (inset) reveal a linear onset at small $V_{\rm ds}$ and a good saturation.
The transfer characteristics of the fabricated DS SB-MOSFET with a gate length of 3 μm measured at room temperature are presented in Fig. 3. A subthreshold swing (SS) of about 69 mV/dec is achieved. A high $I_{\rm on}/I_{\rm off}$ ratio up to 10$^{8}$ is obtained for this transistor at $V_{\rm ds}=-0.5$ V. The ambipolar switching behavior is suppressed by more than 5 orders of magnitude due to the high barrier height for electrons tunneling through at the drain caused by high dose of boron implantation. With $V_{\rm ds}$ reducing from $-$0.1 V to $-$0.5 V, the lowered barrier height at the drain is easier for electrons tunneling, which results in the increase of the n-branch current for about two orders of magnitude. The corresponding output characteristics of this device are shown in the inset of Fig. 3, which reveal a perfectly liner onset at small $V_{\rm ds}$ and a good saturation.
cpl-34-7-078501-fig4.png
Fig. 4. Gate-to-source capacitance $C_{\rm gs}$ with respect to $V_{\rm gs}$ of p-type SB-MOSFET at different frequencies. Here $C_{\rm gs}$ decreases with the increase of frequency at the inverse regime for the channel.
cpl-34-7-078501-fig5.png
Fig. 5. Gate-to-source capacitance $C_{\rm gs}$ of p-type SB-MOSFET with respect to $V_{\rm gs}$ at different $V_{\rm ds}$. The voltage step of the drain to source is $-$0.1 V. Here $C_{\rm gs}$ increases with the decrease of $V_{\rm ds}$ at the inverse and accumulation regimes for the channel. The peak of $C_{\rm gs}$ at the accumulation regime is marked as a black hexagon.
The capacitance of the SB-MOSFET with the gate length of 11 μm was systematically measured in this work. Regarding the $C_{\rm gs}$ measurement, the source and the gate are connected to the LCR meter, and the drain is connected to a dc bias. However, for the $C_{\rm gd}$ measurement, the connections to the source and drain are just exchanged. The capacitance between gate to source at $V_{\rm ds}=0$ V with the frequency differing from 2 kHz to 100 kHz is shown in Fig. 4. At $V_{\rm gs}>1$ V, $C_{\rm gs}$ is decreased nearly to zero when the frequency goes upward to 100 kHz, similar to an MOS capacitor under depletion and inversion. At $V_{\rm gs} < 0$ V, the small dispersion of $C_{\rm gs}$ curves among varied frequencies reveals the low density of interface states at the semiconductor/insulator interface. The capacitance $C_{\rm gs}$ is also significantly affected by the voltage of the drain and source, as shown in Fig. 5. With $V_{\rm ds}$ varying from 0 V to $-$0.9 V, $C_{\rm gs}$ increases in both forward and reverse directions, while the physical explanation differs. At $V_{\rm gs}>0$ V, the channel is inversed to n-type. Since the silicon was p-type at the edge of the channel due to dopant segregation, a p–n junction is created at the reverse bias state. With decreasing the drain voltage, the reverse bias voltage of the p–n junction reduces leading to the decrease of the depletion layer thickness and the increasing capacitance of the depletion layer. Since the capacitance between gate and source can be approximatively regarded as the series connection of the plate capacitance of the gate to channel and the capacitance of the p–n junction, the capacitance $C_{\rm gs}$ increases with the decreasing drain-to-source voltage.
cpl-34-7-078501-fig6.png
Fig. 6. The comparison of $C_{\rm gs}$ and $C_{\rm gs}$ with varied $V_{\rm ds}$. In the reverse direction when the drain-to-source voltage reduces from zero, the gate-to-source capacitance $C_{\rm gs}$ becomes larger while the gate-to-drain capacitance $C_{\rm gd}$ becomes lower. In the forward direction the gate-to-source capacitance increases with reducing $V_{\rm ds}$ due to the capacitance increment of the reverse-biased p–n junction.
At $V_{\rm gs} < 0$ V, the lightly p-doped top silicon is accumulated to the p-type channel due to the reduction of surface potential. When the drain voltage decreases, the potential of the channel is redistributed. The accumulated channel near the drain becomes thinner, while the channel becomes thicker near the source, resulting in the imbalance of the carrier distribution along the channel. Thus the gate-to-drain capacitance is decreased while the gate-to-source capacitance is increased when the drain-to-source voltage reduces from 0 V to $-$0.9 V. The different variation trends of $C_{\rm gs}$ and $C_{\rm gd}$ are compared in Fig. 6. However, with decreasing $V_{\rm gs}$, $C_{\rm gs}$ obtains a maximum and then decreases at the accumulation regime. Since $C_{\rm gs}+C_{\rm gd}=C_{\rm gg} \approx C_{\rm ox}$ at higher $|V_{\rm gs}|$, the increase of $C_{\rm gd}$ can lead to $C_{\rm gs}$ reducing due to the partition. The maximum of capacitance $C_{\rm gs}$ at various $V_{\rm ds}$ is marked as a black hexagon in Fig. 5. A strong linear relationship between $V_{\rm gs}$ and $V_{\rm gd}$ of peaks is shown in Fig. 7 and it can be simply expressed as $V_{\rm gs}=V_{\rm ds}-0.7$ V. This reveals at the accumulation regime when the drain voltage is higher than the gate voltage for about 0.7 V, the distribution of the accumulation area of the channel leads to a maximum $C_{\rm gs}$. For any given semiconductor and metal combination, the sum of the barrier heights on n-type and p-type substrates is expected to be equal to the bandgap.[34] Since the SBH amounts 0.35 eV for epitaxial NiSi$_{2}$ on n-Si and the bandgap is 1.12 eV for Si, the SBH on p-Si for holes should be about 0.77 eV. A strong upward band bending at the interface between highly doped silicon and NiSi$_{2}$ (shown in Fig. 2) results in about 0.7 V voltage droop of the p$^+$ region for S/D. When $V_{\rm gd}=-0.7$ V, there are almost no holes accumulated near the p$^+$ region of the drain while the channel of the source side gains much. Thus the most imbalanced carriers distribution of the channel occurs and $C_{\rm gs}$ becomes the maximum. Furthermore, in this situation the channel will be pinched off near the drain and the transistor will work in the saturation region if $|V_{\rm ds}|$ becomes larger. This indicates that dopant segregation and SBH can tune the build-in voltage for Schottky S/D contacts, thus can affect the pinch-off voltage and saturation current for SB-MOSFETs. On the other hand, when $|V_{\rm ds}|$ is less than 0.4 V, $C_{\rm gs}$ monotonically increases with a negative $V_{\rm gs}$ decreasing, and the curves of $C_{\rm gs}$ and $C_{\rm gd}$ are more similar to $C_{\rm gg}$.
cpl-34-7-078501-fig7.png
Fig. 7. The strong linear relationship between $V_{\rm gs}$ and $V_{\rm ds}$ of $C_{\rm gs}$ peaks.
In summary, p-type SB-MOSFETs with epitaxial NiSi$_{2}$ for S/D contacts and dopant segregation have been fabricated on ultrathin SOI substrates. Good SS of 69 mV/dec and relative high $I_{\rm on}/I_{\rm off}$ ratio have been achieved for SB-MOSFETs. The $C$–$V$ analysis of the accumulation regime reveals that $C_{\rm gs}$ obtains a maximum with decreasing $V_{\rm gs}$ due to the imbalanced redistribution of the channel. By extracting $V_{\rm gs}$ and $V_{\rm ds}$ at $C_{\rm gs}$ peaks we find that the difference of them has a strong relationship with SBH, which indicates that the SBH for NiSi$_{2}$ on silicon and dopant segregation can affect pinch-off voltage and saturation current of the SB-MOSFETs. References Overview and status of metal S/D Schottky-barrier MOSFET technologyHigh Performance P-Channel Schottky Barrier MOSFETs with Self-Aligned PtSi Source/Drain on Thin Film SOI SubstrateThe modulation of Schottky barrier height of NiSi/n-Si Schottky diodes by silicide as diffusion source techniqueSchottky barrier MOSFET structure with silicide source/drain on buried metalFormation and Property of Yttrium and Yttrium Silicide Films as Low Schottcky Barrier material for n-Type SiliconSimultaneous Formation of AlB 2 -Type and ThSi 2 -Type Nanoislands of Er Silicide by Using a Prepatterned Si(001) SubstrateN-Type Schottky Barrier Source/Drain MOSFET Using Ytterbium SilicideSB-MOSFETs in UTB-SOI Featuring PtSi Source/Drain With Dopant SegregationFormation of PtSi Schottky barrier MOSFETs using plasma etchingA High-Performance Source Engineered Charge Plasma-Based Schottky MOSFET on SOIRadio-Frequency Study of Dopant-Segregated n-Type SB-MOSFETs on Thin-Body SOIEffective Schottky barrier lowering in silicon-on-insulator Schottky-barrier metal-oxide-semiconductor field-effect transistors using dopant segregationTuning of NiSi?Si Schottky barrier heights by sulfur segregation during Ni silicidationThe Leakage Current Improvement of a Ni-Silicided SiGe/Si Junction Using a Si Cap Layer and the PAI TechniqueUltrathin Ni Silicides With Low Contact Resistance on Strained and Unstrained Silicon20nm Gate length Schottky MOSFETs with ultra-thin NiSi/epitaxial NiSi2 source/drainSchottky-barrier height and electronic structure of the Si interface with metal silicides: CoSi 2 , NiSi 2 , and YSi 2 Ab Initio Calculation of Vacancies and Interstitials in NiSi 2Thermal Stability and Dopant Segregation for Schottky Diodes With Ultrathin Epitaxial $\hbox{NiSi}_{2 - y}$NiSi2/Si interface chemistry and epitaxial growth modePhysics of ultrathin-body silicon-on-insulator Schottky-barrier field-effect transistorsSchottky Barrier Height Modulation of Nickel Germanide Schottky Diodes by the Germanidation-Induced Dopant Segregation TechniqueDopant segregation in SOI Schottky-barrier MOSFETsMetal Schottky Source/Drain Technology for Ultrathin Silicon-on-Thin-Box Metal Oxide Semiconductor Field Effect TransistorsImage Charge and Dipole Combination Model for the Schottky Barrier Tuning at the Dopant Segregated Metal/Semiconductor InterfaceSimulation of Fabricated 20-nm Schottky Barrier MOSFETs on SOI: Impact of Barrier LoweringPhysics of Semiconductor Devices
[1] Larson J M and Snyder J P 2006 IEEE Trans. Electron Devices 53 1048
[2] Zhu S Y and Li M F 2005 Chin. Phys. Lett. 22 2020
[3] An X et al 2009 Chin. Phys. B 18 4465
[4] Li D Y et al 2007 Chin. Phys. B 16 240
[5] Isogai T et al 2007 Jpn. J. Appl. Phys. 47 3138
[6]Peng Q et al 2015 Acta Phys. Sin. 64 7 (in Chinese)
[7] Liu B B and Cai Q 2013 Chin. Phys. Lett. 30 096801
[8] Zhu S Y et al 2004 IEEE Electron Device Lett. 25 565
[9] Zhang Z, Qiu Z J, Hellstrom P E, Malm G, Olsson J, Lu J, Ostling M and Zhang S L 2008 IEEE Electron Device Lett. 29 125
[10] Woo Y M, Hwang W S and Yoo W J 2015 J. Vac. Sci. Technol. A 33 021307
[11] Bashir F, Loan S A, Rafat M, Alamoud A R M and Abbasi S A 2015 IEEE Trans. Electron Devices 62 3357
[12] Urban C, Emam M, Sandow C, Knoch J, Zhao Q T, Raskin J P and Mantl S 2010 IEEE Electron Device Lett. 31 537
[13] Knoch J, Zhang M, Zhao Q T, Lenk S, Mantl S and Appenzeller J 2005 Appl. Phys. Lett. 87 263505
[14] Zhao Q T, Breuer U, Rije E, Lenk S and Mant S 2005 Appl. Phys. Lett. 86 062108
[15]Yamauchi T, Nishi Y, Tsuchiya Y, Kinoshita A, Koga J and Kato K 2007 IEEE International Electron Devices Meeting (Washington, DC, America 10–12 December 2007) p 963
[16]Huang W, Zhang L C, Gao Y Z and Jin H Y 2005 Acta Phys. Sin. 54 2252 (in Chinese)
[17] Chang J G, Wu C B, Ji X L, Ma H W, Yan F, Shi Y and Zhang R 2012 Chin. Phys. Lett. 29 058501
[18]Shan X N, Huang R, Li Y and Cai Y M 2007 Acta Phys. Sin. 56 4943 (in Chinese)
[19] Knoll L, Zhao Q T, Habicht S, Urban C, Ghyselen B and Mantl S 2010 IEEE Electron Device Lett. 31 350
[20]Knoll L, Zhao Q T, Habicht S, Urban C, Bourdelle K K and Mantl S 2010 Int. Workshop Junction Technol. (Shanghai, China 10–11 May 2010) p 1
[21] Knoll L, Zhao Q T, Luptak R, Trellenkamp S, Bourdelle K K and Mantl S 2012 Solid-State Electron. 71 88
[22] Fujitani H and Asano S 1994 Phys. Rev. B 50 8681
[23] Wang T, Dai Y B, Ouyang S K, Wu J S and Shen H S 2004 Chin. Phys. Lett. 21 2163
[24] Luo J, Gao X D, Qiu Z J, Lu J, Wu D P, Zhao C, Li J F, Chen D P, Hultman L and Zhang S L 2011 IEEE Electron Device Lett. 32 1029
[25] Mi S B, Jia C L, Zhao Q T, Mantl S and Urban K 2009 Acta Mater. 57 232
[26] Knoch J, Zhang M, Appenzeller J and Mantl S 2007 Appl. Phys. A 87 351
[27] An X, Fan C H, Huang R and Zhang X 2009 Chin. Phys. Lett. 26 087304
[28] Knoch J, Zhang M, Feste S and Mantl S 2007 Microelectron. Eng. 84 2563
[29]Zhao Q T, Zhang M, Knoch J and Mantl S 2006 Int. Workshop Junction Technol. (Shanghai, China 15–16 May 2006) p 147
[30] Shima A, Sugii N, Mise N, Hisamoto D, Takeda K I and Torii K 2011 Jpn. J. Apll. Phys. 50 04DC06
[31] Geng L, Magyari-Kope B and Nishi Y 2009 IEEE Electron Device Lett. 30 963
[32]Zhao Q T, Knoll L, Sch(äfer A, Trellenkamp S, Bourdelle K K and Mantl S 2012 Int. Workshop Junction Technol. (Shanghai, China 14–15 May 2012) p 186
[33] Padilla J L, Knoll L, Gamiz F, Zhao Q T, Godoy A and Mantl S 2012 IEEE Trans. Electron Devices 59 1320
[34] Sze S M and Ng K K 2006 Physics of Semiconductor Devices (Hoboken: John Wiley & Sons Inc.) chap 3 p 136