| CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES |
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Temperature-Dependent Effect of Near-Interface Traps on SiC MOS Capacitance |
| Yan-Jing He, Xiao-Yan Tang**, Yi-Fan Jia, Ci-Qi Zhou, Yu-Ming Zhang |
Microelectronics Institute, Xidian University, Xi'an 710071
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| Cite this article: |
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Yan-Jing He, Xiao-Yan Tang, Yi-Fan Jia et al 2018 Chin. Phys. Lett. 35 107301 |
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Abstract A two-dimensional electrical SiC MOS interface model including interface and near-interface traps is established based on the relevant tunneling and interface Shockley–Read–Hall model. The consistency between simulation results and measured data in the different temperatures shows that this interface model can accurately describe the capture and emission performance for near-interface oxide traps, and can well explain the hysteresis-voltage response with increasing temperature, which is intensified by the interaction between deep oxide traps and shallow oxide traps. This also indicates that the near-interface traps result in an increase of threshold-voltage shift in SiC MOSFET with increasing temperature.
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Received: 16 July 2018
Published: 15 September 2018
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| PACS: |
73.40.-c
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(Electronic transport in interface structures)
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77.84.Lf
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(Composite materials)
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73.20.-r
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(Electron states at surfaces and interfaces)
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71.10.Li
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(Excited states and pairing interactions in model systems)
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| Fund: Supported by the Science Challenge Project under Grant No TZ2018003. |
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