Optimizing Design of Breakdown Voltage to Eliminate Back Gate Bias Effect in Silicon-on-Insulator Diode Using Low Doping Buried Layer Support info


	2009, Vol. 26(1): 17303-017303 DOI: 10.1088/0256-307X/26/1/017303

	Optimizing Design of Breakdown Voltage to Eliminate Back Gate Bias Effect in Silicon-on-Insulator Diode Using Low Doping Buried Layer
	HO Chi-Hon¹, LIAO Chien-Nan¹, CHIEN Feng-Tso², TSAI Yao-Tsung¹
	¹Department of Electrical Engineering, National Central University, 300 Jhongda Rd., Jhongli 320, Taoyuan, Taiwan²Department of Electronic Engineering, Feng Chia University, 100 Wenhwa Rd., Seatwen, Taichung 407, Taiwan
	收稿日期 2008-09-18 修回日期 1900-01-01
	Supporting info


	[1] Merchant S, Arnold E, Baumagart H, Mukherjee S, Pein H and Pinker R 1991 Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs p 31 [2] Chung S K, Han S Y, Shin J C, Choi Y I and Kim S B 1996 IEEE Electron Device Letters 17 22 [3] Sun Z, Sun W and Shi L 2005 Solid-State Electron. 49 1896 [4] Huang Y S and Baliga B J 1991 Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs p 27 [5] Merchant S, Arnold E, Baumagart H, Egloff R, Letavic T, Mukherjee S and Pein H 1993 Proceedings of the 5th International Symposium on Power Semiconductor Devices and ICs p 124 [6] Ho C H, Liao C N, Chien F T and Tsai Y T 2008 Jpn. J. Appl. Phys. 47 5369 [7] Nakagawa A, Yamaguchi Y, Yasuhara N, Hirayama K and Funaki H 1996 IEEE Int. Electron. Device Meeting p 477 [8] Tong D W, Benjamin J L and Dell W R V 1986 IEEE Trans. Electron Devices 33 779 [9] ISE TCAD Manuals, release 8.5 [10] Sze S M 1981 Physics of Semiconductor Devices 2$^{nd$ edn (New York: Wiley)