A Compact Spice Model with Verilog-A for Phase Change Memory
CAI Dao-Lin**, SONG Zhi-Tang, LI Xi, CHEN Hou-Peng, CHEN Xiao-Gang
State Key Laboratory of Functional Materials for Informatics, Laboratory of Nanotechnology, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences, Shanghai 200050
A Compact Spice Model with Verilog-A for Phase Change Memory
CAI Dao-Lin**, SONG Zhi-Tang, LI Xi, CHEN Hou-Peng, CHEN Xiao-Gang
State Key Laboratory of Functional Materials for Informatics, Laboratory of Nanotechnology, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences, Shanghai 200050
摘要A compact spice model of the phase change memory with the crystalline fraction as the switching by Verilog-A language is proposed and demonstrated. The model can simulate not only the resistance change by the different electrical pulse, but also the temperature profile and crystalline fraction during programming operation. The simulated resistance as a function of the amplitude of programming voltage pulses is in good agreement with the experimental data.
Abstract:A compact spice model of the phase change memory with the crystalline fraction as the switching by Verilog-A language is proposed and demonstrated. The model can simulate not only the resistance change by the different electrical pulse, but also the temperature profile and crystalline fraction during programming operation. The simulated resistance as a function of the amplitude of programming voltage pulses is in good agreement with the experimental data.
(Vacuum microelectronic device characterization, design, and modeling)
引用本文:
CAI Dao-Lin**;SONG Zhi-Tang;LI Xi;CHEN Hou-Peng;CHEN Xiao-Gang
. A Compact Spice Model with Verilog-A for Phase Change Memory[J]. 中国物理快报, 2011, 28(1): 18501-018501.
CAI Dao-Lin**, SONG Zhi-Tang, LI Xi, CHEN Hou-Peng, CHEN Xiao-Gang
. A Compact Spice Model with Verilog-A for Phase Change Memory. Chin. Phys. Lett., 2011, 28(1): 18501-018501.
[1] Lai S et al 2001 IEEE Int. Electron. Devices Meeting (Washington DC 3–5 December 2001) p 803
[2] Wang K et al 2004 J. Appl. Phys. 96 5557
[3] Kolobov A V et al 2004 Nature Mater. 3 703
[4] Sun Z M et al 2006 Phys. Rev. Lett. 96 055507
[5] Ding S et al 2008 Chin. Phys. Lett. 25 3815
[6] Cobley R A et al 2003 Proc. Inst. Electron. Engin.: Science, Measurement and Technology 150 237
[7] Fantini P et al 2006 IEEE Int. Simulation of Semiconductor Processes and Devices (Monterey, California, USA 6–8 September 2006) p 162
[8] Salamon D et al 2003 IEEE International Workshop on Memory Technology, Design, and Testing (San Jose 28–29 July 2003) p86
[9] Wei X Q et al 2006 IEEE Trans. Electron. Devices 53 56
[10] Ventrice D et al 2007 IEEE Electron. Device Lett. 28 973
[11] Ielmini D et al 2006 IEEE Int. Electron Devices Meeting (San Francisco 11–13 December 2006) p1
[12] Chen F et al 2008 Non-Volatile Memory Technology Symposium p 1
[13] Carslaw H S et al 1959 Conduction of Heat in Solids (Oxford: Clarendon) p 231
[14] Liu Y et al 2009 Jpn. J. Appl. Phys. 48 024502