Hot-Carrier Stress Effects on GIDL and SILC in 90nm LDD-MOSFET with Ultra-Thin Gate Oxide
HU Shi-Gang, HAO Yue, MA Xiao-Hua, CAO Yan-Rong, CHEN Chi, WU Xiao-Feng
School of Microelectronics, Xidian University, Xi'an 710071Key Lab of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, Xidian University, Xi'an 710071
Hot-Carrier Stress Effects on GIDL and SILC in 90nm LDD-MOSFET with Ultra-Thin Gate Oxide
HU Shi-Gang, HAO Yue, MA Xiao-Hua, CAO Yan-Rong, CHEN Chi, WU Xiao-Feng
School of Microelectronics, Xidian University, Xi'an 710071Key Lab of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, Xidian University, Xi'an 710071
摘要Hot-carrier degradation for 90nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4nm) gate oxide is investigated under the low gate voltage stress (LGVS) and peak substrate current (Isub,max) stress. It is found that the degradation of device parameters exhibits saturating time dependence under the two stresses. We concentrate on the effect of these two stresses on gate-induced-drain leakage (GIDL) current and stress induced leakage current (SILC). The characteristics of the GIDL current are used to analyse the damage generated in the gate-to-LDD region during the two stresses. However, the damage generated during the LGVS shows different characteristics from that during Isub,max stress. SILC is also investigated under the two stresses. It is found experimentally that there is a linear correlation between the degradation of SILC and that of threshold voltage during the two stresses. It is concluded that the mechanism of SILC is due to the combined effect of oxide charge trapping and interface traps for the ultra-short gate length and ultra-thin gate oxide LDD NMOSFETs under the two stresses.
Abstract：Hot-carrier degradation for 90nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4nm) gate oxide is investigated under the low gate voltage stress (LGVS) and peak substrate current (Isub,max) stress. It is found that the degradation of device parameters exhibits saturating time dependence under the two stresses. We concentrate on the effect of these two stresses on gate-induced-drain leakage (GIDL) current and stress induced leakage current (SILC). The characteristics of the GIDL current are used to analyse the damage generated in the gate-to-LDD region during the two stresses. However, the damage generated during the LGVS shows different characteristics from that during Isub,max stress. SILC is also investigated under the two stresses. It is found experimentally that there is a linear correlation between the degradation of SILC and that of threshold voltage during the two stresses. It is concluded that the mechanism of SILC is due to the combined effect of oxide charge trapping and interface traps for the ultra-short gate length and ultra-thin gate oxide LDD NMOSFETs under the two stresses.
HU Shi-Gang;HAO Yue;MA Xiao-Hua;CAO Yan-Rong; CHEN Chi;WU Xiao-Feng. Hot-Carrier Stress Effects on GIDL and SILC in 90nm LDD-MOSFET with Ultra-Thin Gate Oxide[J]. 中国物理快报, 2009, 26(1): 17304-017304.
HU Shi-Gang, HAO Yue, MA Xiao-Hua, CAO Yan-Rong, CHEN Chi, WU Xiao-Feng. Hot-Carrier Stress Effects on GIDL and SILC in 90nm LDD-MOSFET with Ultra-Thin Gate Oxide. Chin. Phys. Lett., 2009, 26(1): 17304-017304.
[1] Huang L et al 1998 Microelectron. Reliability 38 1425 [2] Duvvury C et al 1988 IEEE Electron Dev. Lett. 9 579 [3] Lo G Q et al 1991 IEEE Electron Dev. Lett. 125 [4] Chen I C et al 1989 IEEE Electron Dev. Lett. 10 216 [5] Nathan V et al 1993 IEEE Trans. Electron Devices 40 1888 [6] Cheng K G et al 2003 IEEE Electron Dev. Lett. 24 487 [7] Ielmini D et al 2002 IEEE Trans. Electron Devices 49 1723 [8] Ielmini D et al 2006 IEEE Trans. Electron Devices 53 126 [9] Vianello E, Driussi F, Esseni D, Selmi L, Widdershoven Fand Duuren V 2007 IEEE Trans. Electron Devices 54 1953 [10] Driussi F et al 2005 IEEE Trans. Electron Devices 52 949 [11] Ang D S et al 1998 IEEE Trans. Electron Devices 45 149 [12] Raychaudhuri A, Deen M J, Kwan W S and King M I 1996 IEEE Trans. Electron Devices 43 1144 [13] Pan Y et al 1994 IEEE Electron Dev. Lett. 215 [14] Chan V H and Chung J E 1993 International ElectronDevice Meeting (Washington, DC, 6--9 December 1993) p 515 [15] Park Y B and Schroder D K 1998 IEEE Trans. ElectronDevices 45 1361 [16] Heremans P, Bellens R, Groeszeneken G and Maes H E 1998 IEEE Trans. Electron Devices 35 2149 [17] Xiao E, Yuan J S and Yang Hong 2004 IEEE Trans.Device Mater. Reliability 4 92
2009, Vol. 26 
