Numerical Study on a Lateral Double-Gate Tunnelling Field Effect Transistor
HE Jin1,2, BIAN Wei1, TAO Ya-Dong1, LIU Feng2, SONG Yan2, ZHANG Xing1,2
¹Shenzhen Graduate School, Peking University, Senzhen, 518055
²Multi-Project-Wafer (MPW) Center, Institute of Microelectronics, School of Electronic Engineering and Computer Science, Peking University, Beijing 100871
Numerical Study on a Lateral Double-Gate Tunnelling Field Effect Transistor
HE Jin1,2;BIAN Wei1;TAO Ya-Dong1;LIU Feng2;SONG Yan2;ZHANG Xing1,2
¹Shenzhen Graduate School, Peking University, Senzhen, 518055
²Multi-Project-Wafer (MPW) Center, Institute of Microelectronics, School of Electronic Engineering and Computer Science, Peking University, Beijing 100871
Abstract： A novel lateral double-gate tunnelling field effect transistor (DG-TFET) is studied and its performance is presented by a two-dimensional device simulation with code ISE. The result demonstrates that this new tunnelling transistor allows for the steeper sub-threshold swing below 60 mV/dec, the super low supply voltage (operable at VDD<0.3 V) and the rail-to-rail logic (significant on-state current at the drain-source voltage VDS=50 mV) for the aggressive technology assumptions of the availability of high-k/metal stack with equivalent gate oxide thickness EOT=0.24 nm and the work function difference 4.5 eV of materials.
HE Jin;BIAN Wei;TAO Ya-Dong;LIU Feng;SONG Yan;ZHANG Xing;. Numerical Study on a Lateral Double-Gate Tunnelling Field Effect Transistor[J]. 中国物理快报, 2006, 23(12): 3373-3375.
HE Jin, BIAN Wei, TAO Ya-Dong, LIU Feng, SONG Yan, ZHANG Xing,. Numerical Study on a Lateral Double-Gate Tunnelling Field Effect Transistor. Chin. Phys. Lett., 2006, 23(12): 3373-3375.
2006, Vol. 23 
