| Original Articles |
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Numerical Study on a Lateral Double-Gate Tunnelling Field Effect Transistor |
| HE Jin1,2;BIAN Wei1;TAO Ya-Dong1;LIU Feng2;SONG Yan2;ZHANG Xing1,2 |
| ¹Shenzhen Graduate School, Peking University, Senzhen, 518055
²Multi-Project-Wafer (MPW) Center, Institute of Microelectronics, School of Electronic Engineering and Computer Science, Peking University, Beijing 100871
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| Cite this article: |
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HE Jin, BIAN Wei, TAO Ya-Dong et al 2006 Chin. Phys. Lett. 23 3373-3375 |
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Abstract A novel lateral double-gate tunnelling field effect transistor (DG-TFET) is studied and its performance is presented by a two-dimensional device simulation with code ISE. The result demonstrates that this new tunnelling transistor allows for the steeper sub-threshold swing below 60 mV/dec, the super low supply voltage (operable at VDD<0.3 V) and the rail-to-rail logic (significant on-state current at the drain-source voltage VDS=50 mV) for the aggressive technology assumptions of the availability of high-k/metal stack with equivalent gate oxide thickness EOT=0.24 nm and the work function difference 4.5 eV of materials.
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| Keywords:
85.30.Mn
85.30.Tv
85.30.-p
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Published: 01 December 2006
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| PACS: |
85.30.Mn
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(Junction breakdown and tunneling devices (including resonance tunneling devices))
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85.30.Tv
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(Field effect devices)
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85.30.-p
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