| CROSS-DISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY |
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Design of a 1200-V Thin-Silicon-Layer p-Channel SOI LDMOS Device |
| HU Sheng-Dong1,2**, ZHANG Ling1, LUO Xiao-Rong3, ZHANG Bo3, LI Zhao-Ji3, WU Li-Juan3
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1College of Communication Engineering, Chongqing University, Chongqing 400044
2National Laboratory of Analogue Integrated Circuits, Sichuan Institute of Solid-State Circuits, No. 24 Research Institute of China, Electronics Technology Group Corporation, Chongqing 400060
3State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054
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| Cite this article: |
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HU Sheng-Dong, ZHANG Ling, LUO Xiao-Rong et al 2011 Chin. Phys. Lett. 28 128503 |
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Abstract A 1200-V thin-silicon-layer p-channel silicon-on-insulator (SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor is designed. The device named INI SOI p-LDMOS is characterized by a series of equidistant high concentration n+ islands inserted at the interface of a top silicon layer and a buried oxide layer. Accumulation−mode holes, caused by the electric potential dispersion between the device surface and the substrate, are located in the spacing between two neighboring n+ islands, and greatly enhance the electric field of the buried oxide layer and therefore, effectively increase the device breakdown voltage. Based on a 2−µm −thick buried oxide layer and a 1.5-µm −thick top silicon layer, a breakdown voltage of 1224 V is obtained, resulting in the high electric field (608 V/µm ) of the buried oxide layer.
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| Keywords:
85.30.DE
85.30.-Z
85.30.Mn
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Received: 04 July 2011
Published: 29 November 2011
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| PACS: |
85.30.De
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(Semiconductor-device characterization, design, and modeling)
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85.30.-z
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(Semiconductor devices)
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85.30.Mn
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(Junction breakdown and tunneling devices (including resonance tunneling devices))
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