Chin. Phys. Lett.  2010, Vol. 27 Issue (7): 078401    DOI: 10.1088/0256-307X/27/7/078401
CROSS-DISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY |
An Interconnect Bus Power Optimization Method

EN Yun-Fei1,2, ZHU Zhang-Ming1, HAO Yue1

1School of Microelectronics, Xidian University, Xi'an 710071 2National Key Laboratory of Reliability Physics, Guangzhou 510610
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EN Yun-Fei, ZHU Zhang-Ming, HAO Yue 2010 Chin. Phys. Lett. 27 078401
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Abstract

A simple yet accurate interconnect parasitical capacitance model is presented. Based on this model a novel interconnect bus optimization methodology is proposed. Combining wire spacing with wire ordering, this methodology focuses on bus dynamic power optimization with consideration of bus performance requirements. The optimization methodology is verified under a 65 nm technology node and it shows that with 50% slack in the routing space, a 33.03% power saving can be provided by the proposed optimization methodology for an intermediate video bus compared to the 27.68% power saving provided by uniform spacing technology. The proposed methodology is especially suitable for computer-aided design of nanometer scale on-chip buses.

Keywords: 84.30.-r      84.30.Bv     
Received: 08 March 2010      Published: 28 June 2010
PACS:  84.30.-r (Electronic circuits)  
  84.30.Bv (Circuit theory)  
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https://cpl.iphy.ac.cn/10.1088/0256-307X/27/7/078401       OR      https://cpl.iphy.ac.cn/Y2010/V27/I7/078401
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EN Yun-Fei
ZHU Zhang-Ming
HAO Yue
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